Panasonic MN101L Series User Manual page 492

Chapter 16
A/D Converter (ADC)
Sample Hold Time
This LSI contains a sample hold capacitor (C
kΩ).
Set the sample hold time (T
external analog signal output circuit.
It is recommended to select to be T
For example, when R
R = 10 kΩ + 4.0 kΩ = 14 kΩ
C = 2 pF + 16 pF = 18 pF
8RC = 2.0 µs
Set the conversion clock that T
When the setting of sample hold time (ANCTR0.ANSH1-0) is "T
clock (ADCLK) < 1.0 MHz.
External Capacitor
When R is large, the input load will essentially comprise only R
OUT
itance (1000 pF to 1 µF) outside.
It is also recommended that a large-capacitance is added to outside as the protection against noise for the analog
signal.
In this case, ADC may not be possible to follow the analog signal with the large differential coefficient by an
external capacitor affecting as a low-path filter.
When converting a high-speed analog signal, insert a low-impedance buffer.
* When using this ADC, evaluate enough that A/D conversion is ensured the expected precision.
XVI - 14 Operation
AD
) based on the time constant (τ) with C
AD
> 8τ (τ = RC).
AD
= 10 kΩ, T is determined as follows.
OUT AD
* R and C will be simplified to calculate.
> 2.0 µs
AD
External analog signal
outut circuit
R
OUT
Figure:16.3.5 Circuit Example
External analog signal
outut circuit
R
OUT
Figure:16.3.6 Circuit Example with External Capacitor
= 16 pF), input pin capacitor (C
AD
LSI
Equivalent circuit of ADC
R
4.0 kΩ
C
IO
2 pF
, C
AD
LSI
Equivalent circuit of ADC
R
4.0 kΩ
C
IO
2 pF
1000 pF
to 1 µF
= 2 pF) and resistor (R
IO
, C , R and impedance (R
IO AD
× 2", set A/D conversion
ADCLK
AD
C
AD
16 pF
and C by providing a large-capac-
AD IO
AD
C
AD
16 pF
= 4.0
AD
) of
OUT