Panasonic MN101L Series User Manual page 106

Chapter 3
Interrupts
Multiple maskable interrupt control
When MEMCTR.MIESET is "0" and an interrupt is accepted, PSW.MIE is set to "0" and the multiple maskable
interrupt is not occurred.
To enable the multiple interrupts occurrence, set MEMCTR.MIESET to "1" by software before accepting inter-
rupts, or set PSW.MIE to "1" by software in the interrupt handler.
Do not write-access to xICR of maskable interrupts when PSW.MIE is "1".
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When the multiple interrupt acceptance is enabled, be careful not to happen stack overflow.
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III - 12 Overview