Panasonic MN101L Series User Manual page 305

When the value of TMnBC matches the setting value of TMnOC, an interrupt request is gen-
erated at the next count clock and the TMnBC is cleared. So set the TMnOC as follows:
Setting value of the compare register = (Counts till the interrupt request) -1
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When TMnOC1 compare match is selected as a TMnBC clear source and TMnOC2IRQ is
used, the setting value of TMnOC2 should be smaller than the one of TMnOC1.
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If the timer interrupt request bit may have already been set before the timer starts, the timer
interrupt request bit should be cleared.
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When TMnBC is used as a free-counter that counts from "0x0000" to "0xFFFF", set TMnOC1
to "0xFFFF" or set the TMnMD2.TMnBCR to "0".
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Do not change the TMnMD.TMnEN simultaneously with other bits to avoid any error in oper-
ation.
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In 16-bit timer operation, the internal enable signal becomes ON status at the rising edge of
the first count clock after the TMnMD1.TMnEN is set to "1". When it is assumed that the set-
ting value of TMnOC1 is N, the first interrupt is generated at the rising edge of (N+2)th count
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clock. The following interrupts are generated at the rising edge of (N+1)th count clock.
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Be sure to set a count clock of 16-bit timer while a timer interrupt is disabled.
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Chapter 9
16-bit Timer
16-bit Timer IX - 23