Panasonic MN101L Series User Manual page 315

Count Timing of Standard PWM Output (when compare register 1 is set to "0xFFFF")
Count
clock
TMnEN
bit
Compare
register 1
Binary
0000 0001
counter
TMnIO output
(PWM output)
Figure:9.6.3 Count Timing of Standard PWM Output (when compare register 1 is set to "0xFFFF")
When outputting the standard PWM, set the TMnMD2.TMnBCR to "0" to select the full count
overflow as the binary counter clear source and the PWM set source (to "High" state).
.. ..
The TMnOC1 compare match or the TMnOC2 compare match can be selected as a PWM
output reset source ("Low" output) with the TMnMD2.TnPWMSL.
.. ..
The PWM output at the initial state, for Timer 7 and 9, is "Low". It changes to "High" at the
time the PWM operation is selected by setting the TMnMD2.TMnPWM. For Timer 8, it is in
accordance with the setting of the TM8MD2.TM8PWMF and TM8MD2.TM8PWM0.
..
..
When restarting the PWM operation after PWM operation has been stopped, write data to the
preset register to clear the binary counter and the PWM waveform. Otherwise, the PWM
waveform of the first cycle is not guaranteed.
..
..
FFFF
N-1 N N+1 N+2
16-bit Standard PWM Output (with Continuously Variable Duty)
FFFE FFFF 0000 0001
Chapter 9
16-bit Timer
N-1 N N+1
IX - 33