Panasonic MN101L Series User Manual page 309

Count Timing of TMnIO Input (at Both Edges Selected) (Timer 7 and Timer 8)
The binary counter counts up at the falling and rising edges of TMnIO input signal that is divided or not.
TMnIO
input
Count
clock
TMnEN
bit
Compare
register 1
Binary
0000
counter
Interrupt
request
Figure:9.4.2 Count Timing of TMnIO Input (at Both Edges Selected) (Timer 7 and Timer 8)
When selecting the both edge count, the count is executed only at the normal operation
mode (with high-speed oscillation). Also, when setting the TMnMD3.TMnCKSMP to 1 to
select the system clock (SYSCLK), the count is not executed correctly.
..
Input signal from TMnIO should be set to the cycle more than twice the HCLK. When the
other signal with the shorter cycle is input, the count may not be executed correctly.
..
N
0001 0002 0003 N-1 N 0000 0001
Chapter 9
16-bit Timer
16-bit Event Count IX - 27