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Chapter 2
CPU
2.5.3
Oscillation Stabilization Wait Time
The oscillation stabilization wait time is different in the following situations.
1. When the LSI starts up from reset, the wait time is equal to the initial value of the DLYCTR.
2. When transiting from SLOW mode to NORMAL mode, or recovering from HALT2/STOP0 mode, the wait
time can be varied with the DLYCTR.The value of the DLYCTR must be determined for stabilizing the HCLK
oscillation. In this situation, the frequency of OSCSTBCLK is equal to half the of HCLK.
After the oscillation stabilization, the CPU enters the NORMAL mode.
3. When recovering from STOP1 mode, the wait time can be varied with the DLYCTR.
The value of the DLYCTR must be determined for stabilizing the SCLK oscillation.
In this situation, the frequency of OSCSTBCLK is equal to half the of SCLK.
After the oscillation stabilization, the CPU enters the SLOW mode.
OSCSTBCLK is described in the Fig.4.1.1..
II - 30
Reset
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