Panasonic MN101L Series User Manual page 326

Chapter 9
16-bit Timer
Capture Operation with a Trigger of an Interrupt of Timer 0 or 1 (Timer 7 and Timer 8)
A capture trigger of the input capture function is generated at an interrupt signal of Timer 0 or 1.
Count
clock
TMnEN
bit
Compare
register 1
Binary
N
counter
Timer 0, 1
interrupt
Capture
trigger
Capture
register
Figure:9.8.3 Capture Count Timing with a Trigger of an Interrupt of Timer 0 or 1 (Timer 7 and Timer 8)
A capture trigger is generated at an interrupt signal of Timer 0 or 1 when setting the
TMnMD2.TnICT1-0 to "11". Set TMnMD2 and TMnMD4 to select the capture trigger. When
selecting the Timer 0 or 1 interrupt as a capture trigger, the selected edge is invalid.
..
..
A capture trigger is generated by sampling the interrupt signal of Timer 0 or 1 at the capture
clock.
Therefore, the edge of the external interrupt input signal may not be detected when an inter-
..
val of interrupt input signal is shorter than capture clock cycle. To prevent this, please set
count clock of Timer 0 or Timer 1 to be slower than the capture clock cycle.
..
IX - 44 16-bit Timer Capture Function
0000 0001 0111 0112
0000
N
0113 0114 5555 5556
0114
5557 5558 N-1
5558
N