Panasonic MN101L Series User Manual page 224

Chapter 7
I/O Port
Register SC3MD1
Bit name SC3SBTS
1 (*1)
0
*1 When the LSI is the master of Clock-synchronous communication or communicates on IIC bus,
set the P0DIR.P0DIR5 to "1".
Register
Bit name
Register
Bit name
*1 When the LSI outputs the chip select signal, set the P0DIR.P0DIR7 to "1".
VII - 36 Port 0
Table:7.4.7 P05 Function Selection
SC23SEL TM0MD TMIOEN0
SC3SEL2 TM0CK1-0
Other than
0
11
Other than
11
11
-
Other than
11
Table:7.4.8 P06 Function Selection
SC3MD1 SC23SEL
SC3SBIS SC3IOM SC3SEL0
1 0
0 0
Table:7.4.9 P07 Function Selection
SC3MD2 SC23SEL
SC3SBCS
SC3SEL3
EN
1 (*1) 0
0 -
Setup
TM2MD TMIOEN0
TM0OEN TM2CK1-0 TM2OEN
Other than
0
11
Other than
1
11
Other than
11
Other than
11
0
11
Other than
11
Setup
TMIOEN1 TM8MD1
TM8OEN TM8CK1-0
Other than
0 0
Other than
1
-
0
Other than
Setup
TMIOEN1 TM9MD1
TM9OEN TM9CK1-0
Other than
0
10
Other than
1
10
10
0
Other than
10
TMIOSEL0 CLKOUT
TM0IOSE/ CLKOEN/
TM2IOSEL CLKOSEL
0 -/- 0/-
0 0/- 0/-
0 0/- 0/-
1 -/0 0/-
-/0 0/-
0 1/0
-/-
0/-
Function
TMIOSEL1
TM8IOSEL
1-0
- SBI3A
10
01 TM8IO (output)
10
10 01 TM8IO (input)
-
10
Function
TMIOSEL1
TM9IOSEL
1-0
- SBCS3A
00 TM9IO (output)
00 TM9IO (input)
- P07
Function
SBT3A/SCL3A
TM0IO (output)
TM0IO (input)
TM2IO (output)
TM2IO (input)
CLKOUTA
P05
P06