Page 1 Cover MICROCOMPUTER MN103S MN103SA7D/A7G LSI User’s Manual Pub.No.232A7-012E...
Page 3 Request for your special attention and precautions in using the technical information and semiconductors described in this book (1) If any of the products or technical information described in this book is to be exported or provided to non-residents, the laws and regulations of the exporting country, especially, those with regard to security export control, must be observed.
Page 4 A b o u t T h i s M a n u a l Organization This LSI manual describes the features of the MN103SA7 Series, which begins with an overview, fol- lowed by information in the order of CPU basic, interrupt, port, timer, serial, and other peripheral hardware functions.
Page 5: Manual Configuration
Manual Configuration Each section of this manual consists of a title, summary, main text, key information, precautions and warnings, and references.The layout and definition of each section are shown below. Header Chapter number and Chapter title chapter 2 Section title Basic CPU Sub section title 2.8 Reset...
Page 6: Related Manuals
• " Series C Compiler User's Manual: Usage Guide" <Describes the installation, the commands, and options of the C Compiler.> • "MN103S Series C Compiler User's Manual: Language Description" <Describes the syntax of the C Compiler.> • "MN103S Series C Compiler User's Manual: Library Reference"...
Page 7 Chapter Table Contents Chapter 1 Overview Chapter 2 CPU Basics Chapter 3 Clock Generator Chapter 4 Bus Controller Chapter 5 Interrupt Controller Chapter 6 ROM Correction Chapter 7 I/O Ports Chapter 8 8-bit Timer Chapter 9 16-bit Timer Chapter 10 Motor Control PWM Chapter 11 Watchdog Timer Chapter 12 Serial Interface 0 and 1...
Page 9 Chapter 13 Serial Interface 2 Chapter 14 A/D Converter Chapter 15 Regulator Chapter 16 Appendix...
Page 11 Contents Contents...
Page 12: Table Of Contents
Contents Chapter 1 Overview........................ 1-1 1.1 Overview ............................. 1-2 1.1.1 Overview ..........................1-2 1.1.2 Product Summary........................1-2 1.2 Hardware Functions..........................1-3 1.3 Pin Description ............................ 1-9 1.3.1 Pin Configuration ........................1-9 1.3.2 Pin Specification ......................... 1-10 1.3.3 Pin Functions........................1-12 1.4 Block Diagram...........................
Page 13 2.7 Operation Mode ..........................2-21 2.7.1 Overview..........................2-21 2.7.2 Reset Status......................... 2-21 Chapter 3 Clock Generator..................... 3-1 3.1 Overview ............................. 3-2 3.1.1 Functions..........................3-2 3.1.2 Block Diagram ........................3-2 3.2 Control Registers..........................3-3 3.2.1 Clock Generator Control Register ..................3-3 3.2.2 PLL Control Registers ......................
Page 14 5.3 Interrupt Controller Operation ......................5-35 5.3.1 Interrupt Types........................5-35 5.3.2 Interrupt Controller Operation .................... 5-36 5.3.3 Interrupt Controller Setup ....................5-38 5.3.4 Cautions for Programming....................5-39 5.4 Noise Filter Function......................... 5-40 5.4.1 Noise Filter Function List ....................5-40 5.4.2 Noise Filter Block Diagram ....................5-40 5.4.3 Noise Filter Control Registers List ..................
Page 15 7.3.4 Description (Port 4) ......................7-34 7.3.5 Description (Port 5) ......................7-35 7.3.6 Description (Port 6) ......................7-35 7.3.7 Description (Port 7) ......................7-36 7.3.8 Description (Port 8) ......................7-36 7.3.9 Description (Port 9) ......................7-37 7.3.10 Description (Port A)......................7-37 Chapter 8 8-bit Timer......................
Page 16 9.2 Control registers ..........................9-7 9.2.1 Registers..........................9-7 9.2.2 Prescaler Control Registers....................9-9 9.2.3 Programmable Timer Registers ..................9-13 9.2.4 Timer Mode Registers ......................9-19 9.3 Prescaler ............................9-37 9.3.1 Prescaler Operation......................9-37 9.3.2 Setup Example ........................9-38 9.4 Interval Timer........................... 9-39 9.4.1 Interval Timer Function Operation ..................
Page 17 Chapter 10 Motor Control PWM ..................10-1 10.1 Overview ............................10-2 10.1.1 Functions........................... 10-2 10.1.2 Block Diagram ........................10-3 10.2 Control Registers..........................10-4 10.2.1 Control Registers for Motor Control PWM..............10-4 10.2.2 PWM Mode Control Registers ..................10-5 10.2.3 PWM Output Polarity Control Registers ................10-7 10.2.4 PWM Output Control Registers..................
Page 18 12.2.2 Serial Interface Reception and Transmission Registers ........... 12-5 12.2.3 Serial Interface Control Registers..................12-6 12.2.4 Serial Status Registers ...................... 12-8 12.2.5 Serial Clock Selection Registers..................12-10 12.3 Operation............................12-11 12.3.1 Operation ........................12-11 12.3.2 Clock Synchronous Serial Interface ................12-11 12.3.3 Setup Example ........................
Page 19 Chapter 15 Regulator ......................15-1 15.1 Overview ............................15-2 15.1.1 Setup ..........................15-2 15.1.2 Operation .......................... 15-2 Chapter 16 Appendix ......................16-1 16.1 Cautions for Circuit Setup....................... 16-2 16.1.1 General Usage........................16-2 16.1.2 Unused Pins ........................16-2 16.1.3 Power Supply ........................16-5 16.1.4 Power Supply Circuit......................
Page 20 <Contents - 10>...
Page 21: Chapter 1 Overview
Chapter 1 Overview...
Page 22: Chapter 1 Overview
1.1.1 Overview The MN103S is a 32-bit microcontroller combining ease of use intended for programs development in the C lan- guage with a simple, high-performance architecture made possible through pursuit of cost performance. Built around a compact 32-bit CPU with a basic instruction word length of 1 byte, this LSI includes internal mem-...
Page 23: Hardware Functions
Chapter 1 Overview 1.2 Hardware Functions CPU Core MN103S core 4 GB of linear address space (for instructions / data) LOAD/STORE architecture with 5-stage pipeline 46 basic instructions + 30 extension instructions 6 addressing modes Instruction set of 1 byte in word length...
Page 24 Chapter 1 Overview Timer 16 underflow interrupts Timer 17 underflow interrupts <Serial Interface> Serial 0 reception interrupts Serial 0 transmission interrupts Serial 1 reception interrupts Serial 1 transmission interrupts Serial 2 reception interrupts Serial 2 transmission interrupts <PWM> PWM0 overflow interrupts of PWM cycle PWM0 underflow interrupts PWM1 overflow interrupts of PWM cycle PWM1 underflow interrupts...
Page 25 Chapter 1 Overview Timer 3 (8-bit timer for general use) - Interval timer, Timer pulse output, Event count, Cascade connection function (connected to Timer 2) - Count clock source IOCLK, IOCLK/8, IOCLK/32, Timer 0 underflow, Timer 1 underflow, Timer 2 underflow, TM3IO pin input Timer 4 (8-bit timer for general use) - Interval timer, Timer pulse output, Event count, - Count clock source...
Page 26 Chapter 1 Overview - Count clock source IOCLK, IOCLK/8, Timer 0 underflow, Timer 1 underflow, TM10BIO pin input Timer 11 (16-bit timer for general use) - Interval timer, Event count, up/down count, timer output, PWM output (output to 6 ports all at once is possible), input capture, one-shot output, external trigger start - Count clock source IOCLK, IOCLK/8, Timer 4 underflow, Timer 5 underflow,...
Page 27 Chapter 1 Overview A /D Converter - Minimum conversion time 1.0 msec - 16 channels × 3 converters - Use of 3 converters allows simultaneous sampling of 3 phases - A/D conversion start trigger is in synchronization with complementary 3-phase PWM cycle and 16-bit timer Complementary 3-phase PWM output 2 channels...
Page 28 Chapter 1 Overview - Transfer clock source 1/2, 1/4, 1/16, and 1/64 of timer 14 underflow, 1/2, 1/4, 1/16, and 1/64 of timer 15 underflow, 1/2, 1/4, 1/16, and 1/64 of timer 16 underflow, IOCLK/2, IOCLK/4, SBT2 pin - Can be selected as the first bit to be transferred, Any transfer size from 1 to 8 bits can be selected.
Page 29: Pin Description
Chapter 1 Overview 1.3 Pin Description 1.3.1 Pin Configuration P80/IRQ00 P43/TM9BIO P81/IRQ01 P42/TM9AIO P82/IRQ02 P37/TM8BIO P83/IRQ03 P36/TM8AIO TCPOUT P90/ADIN00 P35/TM5IO MN103SA7D P91/ADIN01 P92/ADIN02 P34/TM4IO MN103SA7G P93/ADIN03 P33/TM3IO P32/TM2IO MN103SFA7K P94/ADIN04 P31/TM1IO P27/SBI0 80pinLQFP 0.65 pitch P95/ADIN05 P26/SBT0 P96/ADIN06 P25/SBO0 P97/ADIN07 P24/SBI1 PA0/ADIN08 P23/SBT1...
Page 30: Pin Specification
Chapter 1 Overview 1.3.2 Pin Specification Table:1.3.1 Pin Specification Special Direction Function description functions control control NRST Reset input IRQ04 in/out P10D P10R External interrupt input 4 IRQ05 in/out P11D P11R External interrupt input 5 IRQ06 in/out P12D P12R External interrupt input 6 IRQ07 in/out P13D...
Page 31 Chapter 1 Overview Special Direction Function description functions control control ADIN08 in/out PA0D PA0R AD analog signal input 8 ADIN09 in/out PA1D PA1R AD analog signal input 9 ADIN10 in/out PA2D PA2R AD analog signal input 10 ADIN11 in/out PA3D PA3R AD analog signal input 11 ADIN12...
Page 32: Pin Functions
Chapter 1 Overview 1.3.3 Pin Functions Table:1.3.2 Pin Functions TQFP 48 Name Other Function Function Description Pin No. Power supply pin Power pins for 5 V, digital IO Apply 5 V to all of pins and connect capacitor of over 10 µF between all of the VDD and VSS pins.
Page 33 Chapter 1 Overview TQFP 48 Name Other Function Function Description Pin No. TM1IO I/O port 3 8-bit CMOS I/O ports. TM2IO Each bit can be set individually as either TM3IO input or output by the P3DIR register. TM4IO Pull-up resistor for ech bit can be selected TM5IO individually by the P3PLU register.
Page 34 Chapter 1 Overview TQFP 48 Name Other Function Function Description Pin No. SB00 Output Serial interface Transmission data output pins for serial SB01 transmission data interface 0, 1, and 2. SB02 output pin Select output by the P1DIR and P2DIR regis- ters and serial pin function by the P1MD and P2MD registers.
Page 35 Chapter 1 Overview TQFP 48 Name Other Function Function Description Pin No. ADIN00 Input Analogue input pin Analogue input pins for 16-channel, 10-bit 3 ADIN01 A/D converters. ADIN02 These can be used as normal I/O pins when ADIN03 these are not used as analog input. ADIN04 ADIN05 ADIN06...
Page 36: Block Diagram
Chapter 1 Overview 1.4 Block Diagram 1.4.1 Block Diagram Clock & Internal 32-bit CPU control System control Extension Internal arithmetic unit Interrupt Timers Serial A/Ds control I/Fs Figure:1.4.1 Block Diagram I - 16 Block Diagram...
Page 37: Electrical Characteristics
Chapter 1 Overview 1.5 Electrical Characteristics This LSI manual describes the standard specification. Electrical characteristics given in this section are preliminary and subject to change without notice. When using LSI, contact our sales office for product specifications. Model CMOS LSI Application General-purpose Function...
Page 38: Operating Conditions
Chapter 1 Overview 1.5.2 Operating Conditions Ta= -40 °C to +85 °C VSS = 0.0 V Limits Parameter Symbol Conditions Unit Min. Typ. Max. External supply voltage 1 Vrst DD11 Oscillation Limits Parameter Symbol Conditions Unit Min. Typ. Max. Input frequency FOSC OSC1 OSC0...
Page 39 Chapter 1 Overview VDD = 5.0 V VSS = 0.0 V Ta= -40 °C to +85 °C Limits Parameter Symbol Conditions Unit Min. Typ. Max. External clock input 1 OSCI (OSCO left open) Clock frequency fosc 15.0 High-level pulse width twh1 25.0 Fig.
Page 40: Dc Characteristics
Chapter 1 Overview 1.5.3 DC Characteristics V1 = V or V Output open , PV = 0.0 V DC Characteristics (Upper:M-ROM, Lower:Flash) Limits Parameter Symbol Conditions Unit Typ. Max. VDD = 5.0 V Internal regulator used. FOSC = 10 MHz ( 6 multiplication) Operating circuitry AD0, 1, 2: Continuously convert multiple channels Operating supply current...
Page 41 Chapter 1 Overview = 5.0 V = 0.0 V Ta= -40 °C to +85 °C Limits Parameter Symbol Conditions Unit Min. Typ. Max. Input pins < input: CMOS level> NRST, TEST1 to TEST3 x 0.8 Input voltage High level x 0.2 Input voltage Low level =0 V µA...
Page 42: A/D Converter Characteristics
Chapter 1 Overview 1.5.4 A/D Converter Characteristics =5.0 V = 0.0 V or V Ta= 25 °C A/D0, A/D1, A/D2 Limits Parameter Symbol Conditions Unit Min. Typ. MAx. Resolution Bits Non-linearity error ±3 Sampling time ≥ 200 ns Differential linearity error ±3 A/D conversion clock ≥...
Page 43: Ac Characteristics
Chapter 1 Overview 1.5.5 AC Characteristics Power-On sequence Limits Parameter Symbol Conditions Unit Min. Typ. Max. Reset signal pulse width tRSTW (NRST) Reset release timing tRSTS (NRST) tRSTS NRST tRSTW NRST Figure:1.5.3 Power-On Sequence µF * Insert capacitor of over 0.1 between NRST pin and ground.
Page 44 Chapter 1 Overview =5.0 V = 0.0 V Ta= -40 °C to +85 °C CL= 50 pF Tmclk = 1/MCLK Tsmp = n/IOCLK Interrupt signal input timing n = 4,8 ,16,32 Limits Parameter Symbol Conditions Unit Min. Typ. Max. Interrupt signal pulse width(IRQn) tlRQW1 Tmclk x 3 In not using noise filter...
Page 45 Chapter 1 Overview Power supply detection circuit characteristics Limits Parameter Symbol Conditions Unit Min. Typ. Max. Power supply detection level Rate of change for ∆V ms/V power supply voltage Operation space Reset space X+1.0 X+1.0 time (ms) time (ms) Internal reset signal Figure:1.5.5 Power Supply Detection Level Electrical Characteristics I - 25...
Page 46: Package Dimension
Chapter 1 Overview 1.6 Package Dimension Figure:1.6.1 Package Dimension Sealing material: EPOXY resin Lead material : Cu alloy Lead surface processing : Pd plating I - 26 Package Dimension...
Page 47 Chapter 1 Overview The external dimensions of the package are subject to change. Before using this product, please obtain product specifications from the sales offices. Package Dimension I - 27...
Page 48 Chapter 1 Overview I - 28 Package Dimension...
Page 49: Chapter 2 Cpu Basics
II.. Chapter 2 CPU Basics...
Page 50: Overview
Chapter 2 CPU Basics 2.1 Overview Table: 2.1.1 shows basic specifications. Table:2.1.1 Basic Specifications Data: 32-bit x 4 Load/store architecture Address: 32-bit x 4 (9 registers) Stack pointer: 32-bit x 1 PC: 32-bit × 1 Structure PSW : 16-bit × 1 Load/store architecture (Others) Multiply/divide register: 32-bit x 1...
Page 51: Block Diagram
Chapter 2 CPU Basics 2.2 Block Diagram Table: 2.2.1 shows the block diagram focusing on the CPU. MCLK Clock Address register Data register Clock IOCLK generator Watchdog timer Instruction execution control block Instruction decoder Program Barrel Extension counter shifter function unit block Interrupt Instruction...
Page 52: Chapter 3 Clock Generator
Chapter 2 CPU Basics Table:2.2.1 Block Diagram and Function Blocks Description Uses a clock oscillator circuit driven by an external crystal or ceramic resonator to supply clock signals Clock generator to CPU blocks. Generates addresses for the instructions to be inserted into the instruction queue. Normally Program counter incremented by sequencer indication, but may be set to branch destination address or ALU operation result when branch instructions or interrupts occur.
Page 53: Programming Model
Chapter 2 CPU Basics 2.3 Programming Model 2.3.1 CPU Registers The register set is divided into data registers that are used for arithmetic operations, etc., address registers that are used for pointers, and a stack pointer. This arrangement contributes greatly to the improved performance of the internal architecture, through reduction on instruction code size, improved parallelism in pipeline processing, etc.
Page 54 Chapter 2 CPU Basics Data Register (32-bit x 4) This register can be used generally for all operations. Operations are performed with a 32-bit length and the data size is converted when sending data to and from the memory or by executing of the EXTB or EXTH instructions. When loading data, 8-bit data is zero-extended to 32 bits and send to the register.
Page 55 Chapter 2 CPU Basics Processor Status Word (16-bit x 1) This register indicates the CPU status, and stores flags for operation results and interrupt mask level, etc. Table:2.3.1 Processor Status Word Flag At reset Access R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W Flag Description...
Page 56: Control Registers
Chapter 2 CPU Basics 2.3.2 Control Registers The microcontroller core uses the memory-mapped I/O method to allocate a variety of control registers in a con- trol register address space between x’00008000 and x’00009FFF. The registers listed below are described in this section. For details on other control registers, refer to the respec- tive sections that explain the various built-in peripheral functions.
Page 57: Data Formats
Chapter 2 CPU Basics 2.4 Data Formats Data types can be processed in the four types of bit, byte, halfword and word data. Byte data, halfword data and word data can be handled as signed and unsigned data. The sign bit is MSB. The data in the memory must be aligned data.
Page 58: Instructions
Chapter 2 CPU Basics 2.5 Instructions 2.5.1 Instruction Format The following 11 types of instruction formats are available. 8 bits Format S0 Format S1 imm8 / d8 Format S2 imm16 / d16 /abs16 Format S4 imm32 / d32 /abs32 Format S6 imm48 Format D0 Format D1...
Page 59 Chapter 2 CPU Basics Usually, 8-, 16-, or 32-bit immediate value, displacement, and absolute are connected after the operation code. In the case of the above instruction formats (S2, S4, S6, D2, D3, and D5), two or more of immediate value, displace- ment, and absolute are connected to the operation code.
Page 60: Addressing Modes
Chapter 2 CPU Basics 2.5.2 Addressing Modes The 32-bit microcontroller is equipped with the following 6 addressing modes which are frequently used with compilers. All 6 addressing modes of register direct, immediate value, register indirect, register indirect with dis- placement, absolute and register indirect with index can be used with data transfer group instructions. The 2 addressing modes of register direct and immediate addressing can be used with register operation instructions.
Page 61: Instruction Set
Chapter 2 CPU Basics 2.5.3 Instruction Set The instruction set has a simple organization, and features the generation of compact and optimized code through a C compiler. Basic instructions are one byte in length. Although these instructions are simple and provided with limited data transfer functions (load/store functions), the instructions make it possible to reduce an expansion in code size of assembler programs to the minimum.
Page 62 Chapter 2 CPU Basics Table:2.5.3 Transfer Instructions Instruction Description Register-to-register word data transfer Register-to-memory (or memory-to-register) word data transfer Transfer of immediate value to register MOVBU Register-to-memory (or memory-to-register) byte data transfer (zero expansion) MOVHU Register-to-memory (or memory-to-register) half-word data transfer (zero expansion) MOVM Register-to-memory (or memory-to-registers) data transfer 64-bit sign expansion of word data...
Page 63 Chapter 2 CPU Basics Logic Operation Instructions These instructions are used for the logic operation between source operands, the results of which are stored in a register. All instructions involve flag changes. Table:2.5.6 Logic Operation Instructions Instruction Description Logical product Logical sum Exclusive logical sum Inversion (1’s complement)
Page 64 Chapter 2 CPU Basics Branching Instructions These instructions are used to make flow changes in program execution according to the given conditions. Condi- tional branching instructions are classified into normal conditional branching instructions and loop-dedicated con- ditional branching instructions. A loop-dedicated conditional branching instructions uses a dedicated register, thus minimizing the branching penalty and ensuring high-speed loop execution.
Page 65: Memory Space
Chapter 2 CPU Basics 2.6 Memory Space 2.6.1 Overview This LSI has 4 GB linear address space in which addresses are expressed with 32 bits. The address space consists of the internal ROM space which places built-in memory (ROM/RAM) into the chip and the internal RAM space, the control register space stored various control registers of the microcontroller core, the internal I/O space for the interface of peripheral circuits.
Page 66: Memory Map
Chapter 2 CPU Basics 2.6.2 Memory Map Table: 2.6.1 shows memory map in MN103SA7 series. Refer to 1.1.2 Product Summary in Chapter 1 for ROM and RAM capacity of products. 0x00000000 Internal RAM space 8 KB * 0x00002000 Control register space 36 KB (Instruction place is prohibited.) 0x0000A000...
Page 67: Register Map
Chapter 2 CPU Basics 2.6.3 Register Map Table:2.6.2 shows the register map. Table:2.6.2 Branch Instructions Address IVAR3 IVAR2 IVAR1 IVAR0 x'0000800X Interrupt vector IVAR6 IVAR5 IVAR4 x'0000801X x'0000804X CPUM CPU control x'0000807X ROMCTR x'0000820X Watchdog RSTCTR WDCTR WDBC Clock generator x'0000828X CKCTR x'0000890X...
Page 68 Chapter 2 CPU Basics Address PWMSET0 PWMSEL0 OUTMD0 PWMMD0 x'0000A30X DTMSET0 TCMP0C TCMP0B TCMP0A x'0000A31X PWMDCNT0 BCSTR0 PWMBC0 x'0000A32X PWMSET1 PWMSEL1 OUTMD1 PWMMD1 x'0000A33X DTMSET1 TCMP1C TCMP1B TCMP1A x'0000A34X PWMDCNT1 BCSTR1 PWMBC1 x'0000A35X PWMOFF x'0000A36X AN0CTR1 AN0CTR0 x'0000A40X ADST0 AN0CTREGB AN0CTREGA AN0BUF03 AN0BUF02 AN0BUF01...
Page 69: Operation Mode
Chapter 2 CPU Basics 2.7 Operation Mode 2.7.1 Overview This LSI provides only NORMAL mode as CPU operation mode. Low power consumption mode and other mode are not provided. 2.7.2 Reset Status External Reset Pin Input If the reset pin (NRST) goes “L” level, the chip resets (initializes) itself internally and if the reset pin goes “H” level, the wait for oscillation to stabilize starts by means of the 18-bit binary counter that is driven by the oscilla- tion clock.
Page 70 Chapter 2 CPU Basics Power Supply Detection Reset Reset is generated when the power is on for the internal chip. The power supply voltage reaches to the power sup- ply detection level, the oscillation stabilization wait starts. After the oscillation stabilization wait is completed, the internal reset is released and changes to the normal operation status mode (NORMAL mode).
Page 71: Chapter 3 Clock Generator
III.. Chapter 3 Clock Generator...
Page 72: Overview
Chapter 3 Clock Generator 3.1 Overview The clock generator has an internal PLL circuit and supplies a frequency that is a multiple of the oscillating fre- quency of the oscillator to this microcontroller and peripheral circuit. 3.1.1 Functions Table.3.1.1 shows the functions of the clock generator. Table:3.1.1 Functions of Clock Generator Functions Description...
Page 73: Control Registers
Chapter 3 Clock Generator 3.2 Control Registers 3.2.1 Clock Generator Control Register Table:3.2.1 shows the internal clock supply. Table:3.2.1 Clock Generator Control Register Register Address Access size Description Page PCNT 0x0000AFF2 8, 16 PLL control register III-3 Clock generator CKCTR 0x00008280 8, 16 Clock control register...
Page 74 Chapter 3 Clock Generator Set the register to become the oscillation frequency × PLL multiplication ratio of oscillation frequency = 40 MHz to 60 MHz. When the PLLON and CKSEL [1:0] flags of the PCNT register are changed, reset the PLLSEL flag to “0”...
Page 75: Clock Control Registers
Chapter 3 Clock Generator 3.2.3 Clock Control Registers Clock Control Register (CKCTR: 0x00008280) [8, 16-bit Access Register] IOCK IOCK Flag At reset Access Flag Description Set condition 15-8 SCK1 Reserved Always set “10”. SCK0 00: Setting prohibited IOCK1 01: 1/8 of the clock selected by the PCNT register Set the frequency of IOCLK IOCK0 10: 1/4 of the clock selected by the PCNT register...
Page 76: Operation
Chapter 3 Clock Generator 3.3 Operation 3.3.1 Internal Clock Supply Internal Clock Supply Table:3.3.1 shows the internal clock supply. Table:3.3.1 Internal Clock Supply (Multiplying Power to Oscillation Frequency) Operation clock Setting condition MCK [1 : 0], IOCK [1 : 0] Destination PLL non-selective PLL 4 multiplication PLL 6 multiplication PLL 8 multiplication...
Page 77: Setup Of Input Frequency
Chapter 3 Clock Generator 3.3.2 Setup of Input Frequency Input frequency range of clock generator is 5 MHz (minimum) and 15 MHz (maximum). When the input clock is multiplied, the PLL output frequency (PLLOUT) needs to be set to be 40 MHz to 60 MHz. Table: 3.3.3 shows the input frequency and PLL multiple magnification to be set.
Page 78: Setup Example Of Internal Clock
Chapter 3 Clock Generator Above recommended ranges are based on unit oscillating evaluation of this LSI. After evaluating the actual oscil- lating on the target board, determine the final circuit constant, if necessary. We do not evaluate oscillating of crystal oscillator on this LSI. Set the circuit constant that the oscillator manufac- turer recommends.
Page 79 Chapter 3 Clock Generator Setup Procedure Description (1) Set the multiplication ratio (1) Set the PLL multiplication ratio to 6 by the CKSEL 1 and PCNT (0x0000AFF2) CKSEL0 of the PLL control register (PCNT). bp5: PLLSEL=0 × bp3: PLLON=0 Note: Set the frequency ( oscillation frequceny bp1: CKSEL1=0 multiplication ratio) to 40MHz≤PLLOUT≤60MHz bp0: CKSEL0=1...
Page 80 Chapter 3 Clock Generator III - 10 Operation...
Page 81: Chapter 4 Bus Controller
IV.. Chapter 4 Bus Controller...
Page 82: Overview
Chapter 4 Bus Controller 4.1 Overview The bus controller controls interfacing between the CPU and internal peripheral circuitry. 4.1.1 Functions Table:4.1.1 shows the functions of the bus controller. Table:4.1.1 Functions Functions Description Internal bus Provides high-speed control by means of the system clock (MCLK) Avoids time penalty during storage operation by the store buffer of single stage Supports for storage in the internal peripheral circuitry Store buffer...
Page 83: Operation
Chapter 4 Bus Controller 4.2 Operation 4.2.1 Operation of Bus Controller Bus Configuration The ROM bus between the CPU and internal ROM, the RAM bus between the CPU and internal RAM, the BC bus between the CPU and bus controller, and the I/O bus between the bus controller and internal peripheral cir- cuitry are available as the chip’s internal buses.
Page 84 Chapter 4 Bus Controller Data Access Timing Data access to peripheral circuitry in the internal I/O space is performed in synchronization with IOCLK. Figure: 4.2.2 shows the data access timing chart of the internal I/O space. The address (ABIOA[30:0]), the chip select sig- nal (NABIOCS[n]) and the read enable signal (NABIORE) are output simultaneously at the falling edge of IOCLK(AKIOCLK), while the peripheral circuitry starts to drive the data onto the read data signal (ABIORD[31:0]).
Page 85: Internal Rom Access Control Register
Chapter 4 Bus Controller Store Buffer The bus controller has one store buffer (with a 32-bit data width) to avoid time penalty when conducting storage operation in internal I/O. The CPU storage operation is completed when the address, data and access size are stored in the store buffer, and is executed with no wait states.
Page 86: Setup Example Of Internal Clock
Chapter 4 Bus Controller When the CPU clock (MCLK) is 40 MHz or over, change an access to the internal ROM to 3 cycle access (ROMMC[1:0]=10) by the internal ROM access control register (ROMCTR) before the PLLSEL flag of the PLL control register (PCNT) is switched "0" to "1". The operation that is set to 2 cycle access is not guranteed.
Page 87 Chapter 4 Bus Controller When the CPU clock (MCLK) is 40 MHz or over, change an access to the internal ROM to 3 cycle access (ROMMC[1:0]=10) by the internal ROM access control register (ROMCTR) before the PLLSEL flag of the PLL control register (PCNT) is switched "0" to "1". The operation that is set to 2 cycle access is not guranteed.
Page 88 Chapter 4 Bus Controller IV - 8 Operation...
Page 89: Chapter 5 Interrupt Controller
Chapter 5 Interrupt Controller...
Page 90: Overview
Chapter 5 Interrupt Controller 5.1 Overview The interrupt controllers are comprised of reset interrupts, non-maskable interrupts (NMI), 9 external interrupt pins, and 45 internal interrupts (peripheral function interrupts). 5.1.1 Functions Table:5.1.1 Interrupt Functions Interrupt type Reset interrupt Non-maskable interrupt Level interrupt 0x40000000 0x40000008 0x40000000+ interrupt...
Page 91: Block Diagram
Chapter 5 Interrupt Controller 5.1.2 Block Diagram Block Diagram of Interrupt Controller CPU core Watchdog timer overflow (WDOVFIRQ) GROUP System error Level 0 to 6 GROUP Reserved for system External interrupt 0 GROUP Timer 0 underflow Timer 1 underflow GROUP Timer 2 underflow Timer 3 underflow GROUP...
Page 92 Chapter 5 Interrupt Controller Timer 9 overflow/underflow Timer 9 compare/capture A GROUP Timer 9 compare/capture B Timer 10 overflow/underflow Timer 10 compare/capture A GROUP Timer 10 compare/capture B Timer 11 overflow/underflow Timer 11 compare/capture A GROUP Timer 11 compare/capture B Timer 12 overflow/underflow Timer 12 compare A GROUP...
Page 93 Chapter 5 Interrupt Controller PWM 0 underflow PWM 0 overflow GROUP PWM 1 underflow PWM 1 overflow GROUP External interrupt 1 GROUP External interrupt 2 GROUP External interrupt 3 GROUP External interrupt 4 GROUP External interrupt 5 GROUP External interrupt 6 GROUP External interrupt 7 GROUP...
Page 94 Chapter 5 Interrupt Controller External interrupt 8 GROUP A/D 0 conversion end A/D 0 conversion end B GROUP A/D 1 conversion end A/D 1 conversion end B GROUP A/D 2 conversion end GROUP Timer 14 underflow Timer 15 underflow GROUP Timer 16 underflow Timer 17 underflow GROUP...
Page 95: Control Registers
Chapter 5 Interrupt Controller 5.2 Control Registers The interrupt control registers are comprised of the processor status word (PSW), interrupt vector register, non- maskable control register, group interrupt control register, interrupt accepted group register and external interrupt condition specification register. 5.2.1 Registers List Table: 5.2.1 shows the interrupt control registers.
Page 96 Chapter 5 Interrupt Controller Register Address Access size Functions Page Maskable interrupt G2ICR 0x00008908 8,16 Group 2 interrupt control register V-14 control G3ICR 0x0000890C 8,16 Group 3 interrupt control register V-15 G4ICR 0x00008910 8,16 Group 4 interrupt control register V-15 G5ICR 0x00008914 8,16...
Page 97: Processor Status Word
Chapter 5 Interrupt Controller 5.2.2 Processor Status Word Processor Status Word The interrupt enable flag and interrupt mask level flag are used as interrupt-related flags in the processor status word (PSW). These flags are read- and write-enabled flags. For information about the PSW, refer to [Chapter 2 CPU].
Page 98: Interrupt Vector Register
Chapter 5 Interrupt Controller 5.2.3 Interrupt Vector Register The interrupt vector register is a register that stores the lower 16 bits of the starting address of the processing pro- gram for the accepted level interrupts. The starting addressees of level 0 to 6 of the level interrupts correspond to IVAR0 to IVAR 6.
Page 99 Chapter 5 Interrupt Controller Interrupt Vector Register 2 (IVAR2: 0x00008008) [16-bit access register] Flag IVAR IVAR IVAR IVAR IVAR IVAR IVAR IVAR IVAR IVAR IVAR IVAR IVAR IVAR IVAR IVAR At reset Access Interrupt Vector Register 3 (IVAR3: 0x0000800C) [16-bit access register] Flag IVAR IVAR...
Page 100: Non-Maskable Interrupt Control Register
Chapter 5 Interrupt Controller 5.2.4 Non-Maskable Interrupt Control Register If a NMI interrupt request is issued, The flag corresponding to the request is set. After the NMI interrupt request is accepted, the flag is cleared by software in the NMI interrupt processing program. When the flag is set to “1”, the flag can be cleared by writing “1”.
Page 101: Group N Interrupt Control Registers
Chapter 5 Interrupt Controller 5.2.5 Group n Interrupt Control Registers G2ICR to G30ICR registers are designed to control the level interrupts for groups 2 to 30, respectively. The interrupt priority level is controlled by the GnLV2 to GnLV0 flags. When the interrupt level set in the GnLV2 to GnLV0 flags is smaller than the IM2 to IM0 flags in the PSW, interrupts of the corresponding the interrupt group can be generated.
Page 102 Chapter 5 Interrupt Controller When using LV2 to 0 bits or IE3 to 0 bits in the group n interrupt control register (GnICR) to set the interrupt priority level or specify whether to enable interrupts, make sure that inter- rupts are disabled as indicated below. and 0xf7ff,psw ;...
Page 103 Chapter 5 Interrupt Controller Group 2 Interrupt Control Register (G2ICR: 0x00008908) [8, 16-bit access register] Flag G2LV2 G2LV1 G2LV0 G2IE0 G2IR0 G2ID0 At reset Access Flag Description Set condition G2LV2 Set an interrupt priority level Set a level from 6 to 0 14-12 G2LV1 G2LV0...
Page 104 Chapter 5 Interrupt Controller Group 4 Interrupt Control Register (G4ICR: 0x00008910) [8, 16-bit access register] Flag G4LV2 G4LV1 G4LV0 G4IE1 G4IE0 G4IR1 G4IR0 G4ID1 G4ID0 At reset Access Flag Description Set condition G4LV2 Set an interrupt priority level Set a level from 6 to 0 14-12 G4LV1 G4LV0...
Page 105 Chapter 5 Interrupt Controller Group 6 Interrupt Control Register (G6ICR: 0x00008918) [8, 16-bit access register] Flag G6LV2 G6LV1 G6LV0 G6IE1 G6IE0 G6IR1 G6IR0 G6ID1 G6ID0 At reset Access Flag Description Set condition G6LV2 Set an interrupt priority level Set a level from 6 to 0 14-12 G6LV1 G6LV0...
Page 106 Chapter 5 Interrupt Controller Group 8 Interrupt Control Register (G8ICR: 0x00008920) [8, 16-bit access register] Flag G8LV2 G8LV1 G8LV0 G8IE2 G8IE1 G8IE0 G8IR2 G8IR1 G8IR0 G8ID2 G8ID1 G8ID0 At reset Access Flag Description Set condition G8LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G8LV1...
Page 107 Chapter 5 Interrupt Controller Group 9 Interrupt Control Register (G9ICR: 0x00008924) [8, 16-bit Access Register] Flag G9LV2 G9LV1 G9LV0 G9IE2 G9IE1 G9IE0 G9IR2 G9IR1 G9IR0 G9ID2 G9ID1 G9ID0 At reset Access Flag Description Set condition G9LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G9LV1...
Page 108 Chapter 5 Interrupt Controller Group 10 Interrupt Control Register (G10ICR: 0x00008928) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G10LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G10LV1 G10LV0 Timer 11 compare/capture B interrupt 0: Disabled G10IE2 enable flag...
Page 109 Chapter 5 Interrupt Controller Group 11 Interrupt Control Register (G11ICR: 0x0000892C) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G11LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G11LV1 G11LV0 Timer 12 compare B interrupt enable flag 0: Disabled G11IE2 1: Enabled...
Page 110 Chapter 5 Interrupt Controller Group 12 Interrupt Control Register (G12ICR: 0x00008930) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G12LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G12LV1 G12LV0 Timer 13 compare B interrupt enable flag 0: Disabled G12IE2 1: Enabled...
Page 111 Chapter 5 Interrupt Controller Group 13 Interrupt Control Register (G13ICR: 0x00008934) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G13LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G13LV1 G13LV0 11-10 Serial 0 transmission interrupt enable flag 0: Disabled G13IE1 1: Enabled...
Page 112 Chapter 5 Interrupt Controller Group 15 Interrupt Control Register (G15ICR: 0x0000893C) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G15LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G15LV1 G15LV0 11-10 Serial 2 transmission interrupt enable flag 0: Disabled G15IE1 1: Enabled...
Page 113 Chapter 5 Interrupt Controller Group 17 Interrupt Control Register (G17ICR: 0x00008944) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G17LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G17LV1 G17LV0 11-10 PWM1 binary counter overflow interrupt 0: Disabled G17IE1 enable flag...
Page 114 Chapter 5 Interrupt Controller Group 19 Interrupt Control Register (G19ICR: 0x0000894C) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G19LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G19LV1 G19LV0 11-9 External interrupt 2 interrupt enable flag 0: Disabled G19IE0 1: Enabled...
Page 115 Chapter 5 Interrupt Controller Group 21 Interrupt Control Register (G21ICR: 0x00008954) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G21LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G21LV1 G21LV0 11-9 External interrupt 4 interrupt enable flag 0: Disabled G21IE0 1: Enabled...
Page 116 Chapter 5 Interrupt Controller Group 23 Interrupt Control Register (G23ICR: 0x0000895C) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G23LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G23LV1 G23LV0 11-9 External interrupt 6 interrupt enable flag 0: Disabled G23IE0 1: Enabled...
Page 117 Chapter 5 Interrupt Controller Group 25 Interrupt Control Register (G25ICR: 0x00008964) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G25LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G25LV1 G25LV0 11-9 External interrupt 8 interrupt enable flag 0: Disabled G25IE0 1: Enabled...
Page 118 Chapter 5 Interrupt Controller Group 27 Interrupt Control Register (G27ICR: 0x0000896C) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G27LV2 Set an interrupt priority level Set a level 6 to 0 14-12 G27LV1 G27LV0 11-10 A/D1 conversion complete B interrupt enable 0: Disabled G27IE1 flag...
Page 119 Chapter 5 Interrupt Controller Group 29 Interrupt Control Register (G29ICR: 0x00008974) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition G29LV2 Set an interrupt priority level Set a level from 6 to 0 14-12 G29LV1 G29LV0 11-10 Timer 15 underflow interrupt enable flag 0: Disabled G29IE1...
Page 120: Interrupt Accepted Group Register
Chapter 5 Interrupt Controller 5.2.6 Interrupt Accepted Group Register During a register read, the interrupt accepted group register (IAGR) returns the smallest group number of the groups generating the interrupt levels accepted by the CPU, specified by IM2 to IM0 of the PSW. The GN4 to GN0 flag corresponds to the interrupt group number.
Page 121: External Interrupt Condition Specification Register
Chapter 5 Interrupt Controller 5.2.7 External Interrupt Condition Specification Register This register specifies the external interrupt generation conditions. External Interrupt Condition Specification Register 0 (EXTMDO: 0x00008A80) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition IRQ7 pin trigger condition setting 00: Rising edge IR7TG1 01: Falling edge...
Page 122 Chapter 5 Interrupt Controller External Interrupt Condition Specification Register 1 (EXTMD1: 0x00008A84) [8, 16-bit Access Register] Flag At reset Access Flag Description Set condition 15-2 IRQ8 pin trigger condition setting 00: Rising edge IR8TG1 01: Falling edge IR8TG0 10: “H” level 11: “L”...
Page 123: Interrupt Controller Operation
Chapter 5 Interrupt Controller 5.3 Interrupt Controller Operation 5.3.1 Interrupt Types Reset Interrupts Reset interrupts are interrupts with the highest priority level, and are generated by setting the NRST pin to “L” or writing the CHIPRST flag of the reset control register from “0” to “1”. Registers are initialized by the reset inter- rupt, and a program is executed from 0’x40000000 address.
Page 124: Interrupt Controller Operation
Chapter 5 Interrupt Controller 5.3.2 Interrupt Controller Operation When the CPU accepts an interrupt, first the sequence automatically processed by hardware is executed; then, the interrupt handler processing is processed by software, and the interrupt processing program starts up. The inter- rupt processing sequence is described below.
Page 125 Chapter 5 Interrupt Controller Figure: 5.3.1 shows the interrupt sequence flow. (when not accepting multiple interrupts) The numbers in the fig- ure correspond to the steps in the previous list. Program Handler (pre-processing) Processing for each level Processing for each group Interrupt Processing for each factor...
Page 126: Interrupt Controller Setup
Chapter 5 Interrupt Controller Interrupt Acceptance Timing If an interrupt request occurs part-way through the execution of an instruction, even instructions which require multiple execution cycles such as multiply/divide and other instructions are aborted if possible and the interrupt is accepted.
Page 127: Cautions For Programming
Chapter 5 Interrupt Controller Setup Procedure Description (6) Enable all maskable interrupts. (6) Set the IE flag of PSW to “1” to enable maskable interrupts. bp11: IE = 1 5.3.4 Cautions for Programming External Interrupt Request Signal Maintain the external pin of the interrupt request signal for a minimum of 3 cycles of a system clock (MCLK). The level detection can not be achieved if the signal is not maintained for at least that long.
Page 128: Noise Filter Function
Chapter 5 Interrupt Controller 5.4 Noise Filter Function This LSI incorporates noise filters for external interrupt pins. The noise filter control register can be used to select whether to enable or disable noise filters and sampling frequency. The sampling frequency can be selected from 1/4, 1/8, 1/16, and 1/32 of IOCLK.
Page 129: Noise Filter Control Registers List
Chapter 5 Interrupt Controller 5.4.3 Noise Filter Control Registers List Table; 5.4.2 shows the registers that control the noise filter. Table:5.4.2 Noise Filter Control Registers List Register Address Access size Name Page NFCLK0 0x0000A050 8,16 Sampling clock setting register 0 V-42 NFCLK1 0x0000A052...
Page 130: Noise Filter Sampling Clock Setting Registers
Chapter 5 Interrupt Controller 5.4.4 Noise Filter Sampling Clock Setting Registers Sampling Clock Setting Register 0 (NFCLK0: 0x0000A050) [8, 16-bit access register] Flag NFCK NFCK NFCK NFCK NFCK NFCK NFCK NFCK NFCK NFCK NFCK NFCK NFCK NFCK NFCK NFCK At reset Access Flag Description...
Page 131 Chapter 5 Interrupt Controller Sampling Clock Setting Register 1 (NFCLK1: 0x0000A052) [8, 16-bit access register] Flag NFCK NFCK At reset Access Flag Description Set condition 15-2 Select the IRQ8 sampling clock 00: 1/4 of IOCLK frequency NFCK81 01: 1/8 of IOCLK frequency NFCK80 10: 1/16 of IOCLK frequency 11: 1/32 of IOCLK frequency...
Page 132: Noise Filter Control Registers
Chapter 5 Interrupt Controller 5.4.5 Noise Filter Control Registers This register is used to specify how to control noise filters, that is , specify whether to enable or disable noise fil- ter for external interrupts as desired. Noise Filter Control Register (NFCNT: 0x0000A054) [8, 16-bit access register] Flag CNT8 CNT7...
Page 133: Edge Detection Registers
Chapter 5 Interrupt Controller 5.4.6 Edge Detection Registers This register is used to specify how to control edge detection circuity. It specifies whether to enable or disable both-edge interrupt for each external interrupt pin. Edge Detection Register (IRQEDGESEL: 0x0000A056) [8, 16-bit access register] Flag At reset Access...
Page 134: Noise Filter Operation
Chapter 5 Interrupt Controller 5.4.7 Noise Filter Operation Noise Filter Operation Noise filters can be used for external interrupts by setting the NFCNTn flag of the noise filter control register (NFCNT) to “1”. Each of these noise filter uses the sampling clock to count an external interrupt signal. The filter recognizes such a signal as an interrupt and issues a signal to the internal interrupt controller if the same signal level (“H”...
Page 135: Noise Filter Setup Example
Chapter 5 Interrupt Controller 5.4.8 Noise Filter Setup Example Enable Noise Filter and Both-edge Setup Example Noise remove function (noise filter function) is added to the input signal from P74 pin to generate the external interrupt 0 (IRQ0) at the both-edge. The sampling clock is set to 1/8 of IOCLK. The following shows the setup procedure and description.
Page 136 Chapter 5 Interrupt Controller Disable Noise Filter and programmable active edge Setup Example The external interrupt 0 (IRQ0) is generated at the rising edge of the input signal from P74 pin. Setup Procedure Description (1) Disable the interrupt (1) Set the G2IE0 flag of the G2ICR register to “0” to disable G2ICR(0x00008908) the interrupt.
Page 137: Chapter 6 Rom Correction
VI.. Chapter 6 ROM Correction...
Page 138: Overview
Chapter 6 ROM Correction 6.1 Overview ROM correction provides the function to replace incorrect instructions and data stored in the internal ROM with correct ones. This ROM correction function has 4 channels, each of which can correct 8 bytes of data from a desired address in the internal ROM.
Page 139: Rom Correction Control Registers
Chapter 6 ROM Correction 6.2 ROM Correction Control Registers ROM correction is comprised of the ROM correction address register (RCRnAR) and ROM correction data regis- ter (RCRnDR), and is controlled by the ROM correction control register (RCRCTR). 6.2.1 ROM Correction Control Registers List Table: 6.2.1 shows the registers that control ROM correction.
Page 140: Rom Correction Control Registers
Chapter 6 ROM Correction 6.2.2 ROM Correction Control Registers This register that is a 8-bit readable / writable register controls ROM correction. ROM Correction Control Registers (RCRCTR: 0x7FF00000) [8, 16, 32-bit access register] Flag At reset Access Flag Description Set condition ROM correction mode clear enable 0: ROM correction mode (RCCEN) clear disabled RCMEN...
Page 141: Rom Correction Address Registers
Chapter 6 ROM Correction 6.2.3 ROM Correction Address Registers Each of these registers specifies the address (channel number) at which ROM correction is to be performed. Data can be written only when the RCRWE flag in the ROM correction control register (RCRCTR) is “1”. ROM Correction 0 Address Register (RCROAR: 0x7FF00100) [32-bit access register] Flag AD19...
Page 142 Chapter 6 ROM Correction ROM Correction 2 Address Register (RCR2AR: 0x7FF00120) [32-bit access register] Flag AD19 AD18 AD17 AD16 At reset Access Flag AD15 AD14 AD13 AD12 AD11 AD10 At rest Access Flag Description Set condition ROM correction channel 2 enabled 0: ROM correction disabled RC2CEN 1: ROM correction enabled...
Page 143: Rom Correction Data Registers
Chapter 6 ROM Correction 6.2.4 ROM Correction Data Registers Each of these registers specifies the correction data (channel number) used for ROM correction. Data can be writ- ten only when the RCRWE flag in the ROM correction control register (RCRCTR) is “1”. ROM Correction 0 Data Register (RCR0DR: 0x7FF00108) [32-bit access register] Flag DT63...
Page 144 Chapter 6 ROM Correction ROM Correction 1 Data Register (RCR1DR: 0x7FF00118) [32-bit access register] Flag DT63 DT62 DT61 DT60 DT59 DT58 DT57 DT56 DT55 DT54 DT53 DT52 DT51 DT50 DT49 DT48 At reset Access Flag DT47 DT46 DT45 DT44 DT43 DT42 DT41 DT40...
Page 145 Chapter 6 ROM Correction ROM Correction 2 Data Register (RCR2DR: 0x7FF00128) [32-bit access register] Flag DT63 DT62 DT61 DT60 DT59 DT58 DT57 DT56 DT55 DT54 DT53 DT52 DT51 DT50 DT49 DT48 At reset Access Flag DT47 DT46 DT45 DT44 DT43 DT42 DT41 DT40...
Page 146 Chapter 6 ROM Correction ROM Correction 3 Data Register (RCR3DR: 0x7FF00138) [32-bit access register] Flag DT63 DT62 DT61 DT60 DT59 DT58 DT57 DT56 DT55 DT54 DT53 DT52 DT51 DT50 DT49 DT48 At reset Access Flag DT47 DT46 DT45 DT44 DT43 DT42 DT41 DT40...
Page 147: Rom Correction Operation
Chapter 6 ROM Correction 6.3 ROM Correction Operation ROM correction is designed to supply the microcontroller core (CPU, DMAC) with corrected data by replacing part of data - data read from internal ROM as a result of access by the microcontroller core (CPU, DMAC) - with the correction data stored in a ROM correction data register, thus allowing temporary correction of programs and data stored in internal ROM.
Page 148 Chapter 6 ROM Correction Setting ROM Correction Table: 6.3.1 shows setting ROM correction. Table:6.3.1 Setting ROM Correction Description RCRCTR value Checking the ROM correction control register (RCRCTR) 0x00 Check that the RCRCTR register is set to “0x00”. When the RCRCTR register is set to “0x04” (during ROM correction enabled status), reset ROM correction.
Page 149: Rom Correction Setting Example
Chapter 6 ROM Correction 6.3.2 ROM Correction Setting Example ROM Correction Setting Example (1) 8 bytes of data stored in the internal ROM addressees “0x40002000 ~ 0x40002007” are corrected by ROM cor- rection channel 0 as indicated in the following. Lower 3 bits Before change After change...
Page 150 Chapter 6 ROM Correction ROM Correction Setting Example (2) 8 bytes of data stored in the internal ROM addressees “0x40006543 ~ 0x4000654A” are corrected by ROM cor- rection channel 0 as indicated in the following. Lower 3 bits Before change After change →...
Page 151: Cautions For Programming
Chapter 6 ROM Correction 6.3.3 Cautions for Programming ROM correction can be programmed such that 8 bytes of data starting with an address that is a multiple of 8 are changed through 1 channel. For instance, when 8-byte data change from x’40006543 is selected, 8-byte data change from x’40006540 to x’40006547 and from x’40006548 to x’4000654F can- not be selected.
Page 152 Chapter 6 ROM Correction VI - 16 ROM Correction Operation...
Page 153: Chapter 7 I/O Port
VII.. Chapter 7 I/O Port...
Page 154: Overview
Chapter 7 I/O Port 7.1 Overview A total of 61 pins on this LSI, including those shared with special function pins, are allocated for the I/O ports of port 0 to port A. Each I/O port is allocated in the internal I/O space, and can access by bytes or bits the same as RAM.
Page 155: Status At Reset
Chapter 7 I/O Port 7.1.1 Status at Reset Table: 7.1.2 shows the I/O port status at reset. Table:7.1.2 I/O Port Status at Reset Port I/O mode Pull-up resistor I/O port, special functions Port 1 Input mode No pull-up resistor I/O port Port 2 Input mode No pull-up resistor...
Page 156: Block Diagram
Chapter 7 I/O Port 7.1.2 Block Diagram Block Diagram (P10, P11, P12, P13, P14, P80, P81, P82, P83) P10 to P14, P80 to P83 are dual-purpose ports that also serve as external interrupt pins; IRQ00 to 08. PnPLU Internal data bus PnOUT P10 to P14 P80 to P83...
Page 157: Chapter 8 8-Bit Timer 8
Chapter 7 I/O Port Block Diagram (P16, P31, P32, P33, P34, P35, P51) P16, P31 to P35, P51 are dual-purpose ports that serve as 8-bit timer pins. Internal data bus PnPLU PnOUT P31 to P35 TM1IO to TM5IO TM7IO to TM17IO PnMD PnDIR TM1IO to TM5IO...
Page 158: Chapter 9 16-Bit Timer
Chapter 7 I/O Port Block Diagram (P72, P73) P72, P73 are dual-purpose that serve as 16-bit timer pins. Internal data bus P7PLU P7OUT P72, P73 TM11IO0, TM11IO1 P7MD P7DIR TM11IO0, TM11IO1 P7IN indicates 1 bit of a register. P... Figure:7.1.5 Block Diagram (P72 to P73) Block Diagram (P52, P53, P54, P55, P56, P57) P52 to P57 are dual-purpose ports that serve as PWM0 output pins.
Page 159 Chapter 7 I/O Port Block Diagram (P62, P63, P64, P65, P66, P67) P62 to P67 are dual-purpose ports that serve as PWM1 output pins. Internal data bus P6PLU P6OUT P62 to P67 PWM10, 11, 12 NPWM10, 11, 12 P6DIR PWMHZ1 (PWM1 Hz control) P6MD P6IN...
Page 160: Control Registers
Chapter 7 I/O Port 7.2 Control Registers Port 1 to port A are controlled by the data output register (PnOUT), the data input register (PnIN), the I/O direc- tion control register (PnDIR), the pull-up resistor control register (PnPLU), and registers that control special func- tion pins (PnMD).
Page 161 Chapter 7 I/O Port Register Address Access size Function Page P6OUT 0x0000A006 Port 6 output register VII-22 P6IN 0x0000A016 Port 6 input register VII-22 Port 6 P6DIR 0x0000A026 Port 6 I/O control register VII-22 P6MD 0x0000A036 Port 6 output mode register VII-23 P6PLU 0x0000A046...
Page 162: Control Registers
Chapter 7 I/O Port 7.2.2 Control Registers Port 1 Output Register (P1OUT: 0x0000A001) [8-bit access register] Flagº P17O P16O Reser P14O P13O P12O P11O P10O At reset Access Flag Description Set condition P17O Output data Output data P16O Reserved Write "0" P14O Output data Output data...
Page 163 Chapter 7 I/O Port Port 1 I/O Control Register (P1DIR: 0x0000A021) [8-bit access register] Flag P17D P16D Reser P14D P13D P12D P11D P10D At reset Access Flag Description Set condition P17D I/O mode selection 0: Input mode 1: Output mode P16D Reserved Write "0"...
Page 164 Chapter 7 I/O Port Port 1 Pull-up Resistor Control Mode Register (P1PLU: 0x0000A041) [8-bit access register] Flag P17R P16R Reser P14R P13R P12R P11R P10R At reset Access Flag Description Set condition P17R Pull-up resistor selection 0: Not added 1:Added P16R Reserved Write "0"...
Page 165 Chapter 7 I/O Port Port 2 Output Register (P2OUT: 0x0000A002) [8-bit access register] Flag P27O P26O P25O P24O P23O P22O P21O P20O At reset Access Flag Description Set condition P27O Output data Output data P20O Port 2 Input Register (P2IN: 0x0000A012) [8-bit access register] Flag P27I P26I...
Page 166 Chapter 7 I/O Port Port 2 Output Mode Register (P2MD: 0x0000A032) [8-bit access register] Flag P26M P25M P23M P22M P20M At reset Access Flag Description Set condition Output pin setting 0: P26 pin P26M 1: SBT0 pin Output pin setting 0: P25 pin P25M 1: SBO0 pin...
Page 167 Chapter 7 I/O Port Port 3 Output Register (P3OUT: 0x0000A003) [8-bit access register] Flag P37O P36O P35O P34O P33O P32O P31O Reser At reset Access Flag Description Set condition P37O Output data Output data P31O Reserved Write "0" Port 3 Input Register (P3IN: 0x0000A013) [8-bit access register] Flag P37I P36I...
Page 168 Chapter 7 I/O Port Port 3 Output Mode Register (P3MD: 0x0000A033) [8-bit access register] Flag P37M P36M P35M P34M P33M P32M P31M Reser At reset Access Flag Description Set condition Output pin setting 0: P37 pin P37M 1: TM8BI0 pin Output pin setting 0: P36 pin P36M...
Page 169 Chapter 7 I/O Port Port 4 Output Register (P4OUT: 0x0000A004) [8-bit access register] Flag P47O P46O Reser Reser P43O P42O Reser Reser At reset Access Flag Description Set condition P47O Output data Output data P46O Reserved Write "0" P43O Output data Output data P42O Reserved...
Page 170 Chapter 7 I/O Port Port 4 I/O Control Register (P4DIR: 0x0000A024) [8-bit access register] Flag P47D P46D Reser Reser P43D P42D Reser Reser At reset Access Flag Description Set condition P47D I/O mode selection 0: Input mode 1: Output mode P46D Reserved Write "0"...
Page 171 Chapter 7 I/O Port Port 4 Pull-up Resistor Control Register (P4PLU: 0x0000A044) [8-bit access register] Flag P47R P46R Reser Reser P43R P42R Reser Reser At reset Access Flag Description Set condition P47D Pull-up resistor selection 0: No added 1: Added P46D Reserved Write "0"...
Page 172 Chapter 7 I/O Port Port 5 Output Register (P5OUT: 0x0000A005) [8-bit access register] Flag P57O P56O P55O P54O P53O P52O P51O Reser At reset Access Flag Description Set condition P57O Output data Output data P51O Reserved Write "0" Port 5 Input Register (P5IN: 0x0000A015) [8-bit access register] Flag P57I P56I...
Page 173 Chapter 7 I/O Port Port 5 Output Mode Register (P5MD: 0x0000A035) [8-bit access register] Flag P57M P56M P55M P54M P53M P52M P51M Reser At reset Access Flag Description Set condition Output pin setting 0: P57 pin P57M 1: NPWM02 pin Output pin setting 0: P56 pin P56M...
Page 174 Chapter 7 I/O Port Port 6 Output Register (P6OUT: 0x0000A006) [8-bit access register] Flag P67O P66O P65O P64O P63O P62O Reser Reser At reset Access Flag Description Set condition P67O Output data Output data P62O Reserved Write "0" Port 6 Input Register (P6IN: 0x0000A016) [8-bit access register] Flag P67I P66I...
Page 175 Chapter 7 I/O Port Port 6 Output Mode Register (P6MD: 0x0000A036) [8-bit access register] Flag P67M P66M P65M P64M P63M P62M At reset Access Flag Description Set condition Output pin setting 0: P67 pin P67M 1: NPWM12 pin Output pin setting 0: P66 pin P66M 1: PWM12 pin...
Page 176 Chapter 7 I/O Port Port 7 Output Register (P7OUT: 0x0000A007) [8-bit access register] Flag Rese Rese Rese Rese P73O P72O rved rved rved rved At reset Access Flag Description Set condition Reserved Write "0" P73O Output data Output data P72O Port 7 Input Register (P7IN: 0x0000A017) [8-bit access register] Flag Rese...
Page 177 Chapter 7 I/O Port Port 7 Output Mode Register (P7MD: 0x0000A037) [8-bit access register] Flag Reser Reser Reser Reser P73M P72M At reset Access Flag Description Set condition Reserved Write "0" Output pin setting 0: P73 pin P73M 1: TM11IO1 pin Output pin setting 0: P72 pin P72M...
Page 178 Chapter 7 I/O Port Port 8 Output Register (P8OUT: 0x0000A008) [8-bit access register] Flag Reser Reser Reser Reser P83O P82O P81O P80O At reset Access Flag Description Set condition Reserved Write "0" P83O Output data Output data P80O Port 8 Input Register (P8IN: 0x0000A018) [8-bit access register] Flag Rese Rese...
Page 179 Chapter 7 I/O Port Port 8 Pull-up Resistor Control Register (P8PLU: 0x0000A048) [8-bit access register] Flag Rese Rese Rese Rese P83R P82R P81R P80R rved rved rved rved At reset Access Flag Description Set condition Reserved Write "0" P83R Pull-up resistor selection 0: Not added 1: Added P80R...
Page 180 Chapter 7 I/O Port Port 9 Output Register (P9OUT: 0x0000A009) [8-bit access register] Flag P97O P96O P95O P94O P93O P92O P91O P90O At reset Access Flag Description Set condition P97O Output data Output data P90O Port 9 Input Register (P9IN: 0x0000A019) [8-bit access register] Flag P97I P96I...
Page 181 Chapter 7 I/O Port Port 9 Output Mode Register (P9MD: 0x0000A039) [8-bit access register] Flag P97M P96M P95M P94M P93M P92M P91M P90M At reset Access Flag Description Set condition Output pin setting 0: P97 pin P97M 1: ADIN07 pin Output pin setting 0: P96 pin P96M...
Page 182 Chapter 7 I/O Port Port A Output Register (PAOUT: 0x0000A00A) [8-bit access register] Flag PA7O PA6O PA5O PA4O PA3O PA2O PA1O PA0O At reset Access Flag Description Set condition PA7O Output data Output data PA0O Port A Input Register (PAIN: 0x0000A01A) [8-bit access register] Flag PA7I PA6I...
Page 183 Chapter 7 I/O Port Port A Output Mode Register (PAMD: 0x0000A03A) [8-bit access register] Flag PA7M PA6M PA5M PA4M PA3M PA2M PA1M PA0M At reset Access Flag Description Set condition Output pin setting 0: PA7 pin PA7M 1: ADIN15 pin Output pin setting 0: PA6 pin PA6M...
Page 184: Ports
Chapter 7 I/O Port 7.3 Ports 7.3.1 Description (Port 1) General Port Setup Each bit can be set individually as either an input or output by the port 1 I/O control register (P1DIR). The control flag of the P1DIR register is set to “1” for output mode and to “0” for input mode. To read input data of a pin, set the control flag of the P1DIR to “0”...
Page 185: Description (Port 2)
Chapter 7 I/O Port 7.3.2 Description (Port 2) General Port Setup Each bit can be set individually as either an input or output by the port 2 I/O control register (P2DIR). The control flag of the P2DIR register is set to “1” for output mode, and to “0” for input mode. To read input data of a pin, set the control flag of the P2DIR register to “0”...
Page 186: Description (Port 3)
Chapter 7 I/O Port 7.3.3 Description (Port 3) General Port Setup Each bit can be set individually as either an input or output by the port 3 I/O control register (P3DIR). The control flag of the P3DIR register is set to “1” for output mode, and to “0” for input mode. To read input data of a pin, set the control flag of the P3DIR register to “0”...
Page 187: Description (Port 5)
Chapter 7 I/O Port 7.3.5 Description (Port 5) General Port Setup Each bit can be set individually as either an input or output by the port 5 I/O control register (P5DIR). The control flag of the P5DIR is set to “1” for output mode, and to “0” for input mode. To read input data of a pin, set the control flag of the P5DIR register to “0”...
Page 188: Description (Port 7)
Chapter 7 I/O Port 7.3.7 Description (Port 7) General Port Setup Each bit can be set individually as either an input or output by the port 7 I/O control register (P7DIR). The control flag of the P7DIR register is set to “1” for output mode, and to “0” for input mode. To read input data of a pin, set the control flag of the P7DIR register to “0”...
Page 189: Description (Port 9)
Chapter 7 I/O Port 7.3.9 Description (Port 9) General Port Setup Each bit can be set individually as either an input or output by the port 9 I/O control register (P9DIR). The control flag of the P9DIR register is set to “1” for output mode, and to “0” for input mode. To read input data of a pin, set the control flag of the P9DIR register to “0”...
Page 190 Chapter 7 I/O Port VII - 38 Ports...
Page 191: Chapter 8 8-Bit Timer
VIII.. Chapter 8 8-bit Timer...
Page 192: Overview
Chapter 8 8-bit Timer 8.1 Overview This LSI contains 12 general purpose 8-bit timers (timer 0 to timer 7, timer14 to timer17). Timer 14 to timer16 can be used as baud rate timers of serial interface. 8.1.1 Functions Table:8.1.1 shows functions that can be used with each timer. Table:8.1.1 Timer Functions Timer 0 Timer 1...
Page 193 Chapter 8 8-bit Timer Timer 14 Timer 15 Timer 16 Timer 17 Page Interrupt cause NTMIRQ14 NTMIRQ15 NTMIRQ16 NTMIRQ17 Interval timer VIII-32 Timer output VIII-36 Event count VIII-38 Baud rate timer VIII-32 Cascade connection Connect with timer 14 Connect with timer 15 Connect with timer 16 VIII-40 Counter source...
Page 194: Connection Diagram
Chapter 8 8-bit Timer 8.1.2 Connection Diagram 8-bit Timer Connection Diagram (Timer 0 to 3) External prescaler control register TMEXPSC8 Reset Prescaler TM03PSC External prescaler IOCLK 1/8, 32 1/128 Prescaler control register IOCLK TM0IN0 TM0CI NTMIRQ0 TM0IN1 NTMIRQ0 TM0IN2 Timer interrupt 0 TM0IN3 Timer 0 TM0IN4...
Page 195 Chapter 8 8-bit Timer 8-bit Timer Connection Diagram (Timer 4 to 7) External prescaler register TMEXPSC8 Reset Prescaler TM47PSC External prescaler IOCLK 1/8, 32 1/128 Prescaler control register IOCLK TM4IN0 TM4CI NTMIRQ4 TM4IN1 NTMIRQ4 TM4IN2 Timer interrupt 4 TM4IN3 Timer 4 TM4IN4 TMOUT4 TMOUT4...
Page 196 Chapter 8 8-bit Timer 8-bit Timer Connection Diagram (Timer 14 to 17) External prescaler register TMEXPSC8 Reset Prescaler TM1417PSC External prescaler IOCLK 1/8, 32 1/128 Prescaler control register IOCLK TM14IN0 TM14CI NTMIRQ14 TM14IN1 NTMIRQ14 TM14IN2 Timer interrupt 14 TM14IN3 Timer 14 TM14IN4 TMOUT14 TM14IN5...
Page 197: Block Diagram
Chapter 8 8-bit Timer 8.1.3 Block Diagram 8-bit Timer Block Diagram Timer n ( n = 0, 1, 2, 3, 4, 5, 6, 7, 14, 15, 16, 17) TMnIN0 TMnIN1 TMnIN2 TMnIN7 TMnBR Base register TMnCI Lower timer Count operation enable Reload casucading signa Load...
Page 198: Control Registers
Chapter 8 8-bit Timer 8.2 Control Registers Timer 0 to timer 7 and timer 14 to timer 17 consist of the binary counter (TMnBC) and the base register (TMnBR), and are controlled by the mode register (TMnMD). When the prescaler output is selected as the count clock source of timer 0 to 7, they should be controlled by the prescaler control register.
Page 199 Chapter 8 8-bit Timer Register Address Access size Function Page TM4BR 0x0000A1A8 TImer 4 base register VIII-14 TM4BC 0x0000A1B0 Timer 4 binary counter VIII-16 TM4MD 0x0000A1A0 Timer 4 mode register VIII-22 Timer 4 G5ICR 0x00008914 8,16 Group 5 interrupt control register V-16 P3MD 0x0000A033...
Page 200 Chapter 8 8-bit Timer Register Address Access size Function Page TM17BR 0x0000A1CD Timer 17 base register VIII-15 TM17BC 0x0000A1D5 Timer 17 binary counter VIII-17 TM17MD 0x0000A1C5 Timer 17 mode register VIII-29 Timer 17 G30ICR 0x0000897B 8,16 Group 30 interrupt control register V-31 P1MD 0x0000A031...
Page 201: Prescaler Control Registers
Chapter 8 8-bit Timer 8.2.2 Prescaler Control Registers When the prescaler output is selected as the count clock source for 8-bit timer, these registers should be con- trolled. Prescaler Control Register 1 (TM03PSC : 0x0000A198) [8,16-bit Access Register] Flag TMPSC At reset Access Flag...
Page 202 Chapter 8 8-bit Timer External Prescaler Control Register 0 (TMEXPSC8 : 0x0000A19C) [8,16-bit Access Register] Flag TM16IN TM14IN TM6IN TM4IN TM2IN TM0IN PSCNE At reset Access Flag Description Set condition Timer 16 count clock source selection 0: Can not be used TM16IN 1: IOCLK/128 Timer 14count clock source selection...
Page 203: Programmable Timer Registers
Chapter 8 8-bit Timer 8.2.3 Programmable Timer Registers Timer 0 to timer 7,timer 14 to timer 17 each have 8-bit programmable timer registers. Programmable timer registers consist of the base register and binary counter. Timer n base registers set the initial value of the timer n binary counter (TMnBC) and the underflow period. The value of timer n base register (TMnBR) setting is loaded into TMnBC under the following conditions: •...
Page 204 Chapter 8 8-bit Timer Timer 4 Base Register (TM4BR: 0x0000A1A8) [8-bit Access Register] Flag At reset Access Timer 5 Base Register (TM5BR: 0x0000A1A9) [8-bit Access Register] Flag At reset Access Timer 6 Base Register (TM6BR: 0x0000A1AC) [8-bit Access Register] Flag At reset Access Timer 7 Base Register (TM7BR: 0x0000A1AD) [8-bit Access Register]...
Page 205 Chapter 8 8-bit Timer Timer 15 Base Register (TM15BR: 0x0000A1C9) [8-bit Access Register] Flag TM15 TM15 TM15 TM15 TM15 TM15 TM15 TM15 At reset Access Timer 16 Base Register (TM16BR: 0x0000A1CC) [8-bit Access Register] Flag TM16 TM16 TM16 TM16 TM16 TM16 TM16 TM16...
Page 206 Chapter 8 8-bit Timer Timer 2 Binary Counter (TM2BC: 0x0000A194) [8-bit Access Register] Flag At reset Access Timer 3 Binary Counter (TM3BC: 0x0000A195) [8-bit Access Register] Flag At reset Access Timer 4 Binary Counter (TM4BC: 0x0000A1B0) [8-bit Access Register] Flag At reset Access Timer 5 Binary Counter (TM5BC: 0x0000A1B1) [8-bit Access Register]...
Page 207 Chapter 8 8-bit Timer Timer 7 Binary Counter (TM7BC: 0x0000A1B5) [8-bit Access Register] Flag At reset Access Timer 14 Binary Counter (TM14BC: 0x0000A1D0) [8-bit Access Register] Flag TM14 TM14 TM14 TM14 TM14 TM14 TM14 TM14 At reset Access Timer 15 Binary Counter (TM15BC: 0x0000A1D1) [8-bit Access Register] Flag TM15 TM15...
Page 208: Timer Mode Registers
Chapter 8 8-bit Timer 8.2.4 Timer Mode Registers Timer mode registers are readable/writable 8-bit registers that control timer 0 to timer 7 and timer 14 to 17. Timer 0 Mode Register (TM0MD: 0x0000A180) [8-bit Access Register] Flag At reset Access Flag Description Set condition...
Page 209 Chapter 8 8-bit Timer Timer 1 Mode Register (TM1MD: 0x0000A181) [8-bit Access Register] Flag At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM1CNE 1: Operation enabled Timer initialization 0: Normal operation TM1LDE 1: Initialization TM1BR value is loaded into TM1BC. Timer output 1 is set to “L” level. Count clock source selection 000: IOCLK 001: IOCLK/8...
Page 210 Chapter 8 8-bit Timer Timer 2 Mode Register (TM2MD: 0x0000A184) [8-bit Access Register] Flag At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM2CNE 1: Operation enabled Timer initialization 0: Normal operation TM2LDE 1: Initialization TM2BR value is loaded into TM2BC. Timer output 2 is set to “L” level. Count clock source selection 000: IOCLK 001: IOCLK/8...
Page 211 Chapter 8 8-bit Timer Timer 3 Mode Register (TM3MD: 0x0000A185) [8-bit Access Register] Flag At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM3CNE 1: Operation enabled Timer initialization 0: Normal operation TM3LDE 1: Initialization TM3BR value is loaded into TM3BC. Timer output 3 is set to “L” level. Count clock source selection 000: IOCLK 001: IOCLK/8...
Page 212 Chapter 8 8-bit Timer Timer 4 Mode Register (TM4MD: 0x0000A1A0) [8-bit Access Register] Flag At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM4CNE 1: Operation enabled Timer initialization 0: Normal operation TM4LDE 1: Initialization TM4BR value is loaded into TM4BC. Timer output 4 is set to “L” level. Count clock source selection 000: IOCLK 001: IOCLK/8...
Page 213 Chapter 8 8-bit Timer Timer 5 Mode Register (TM5MD: 0x0000A1A1) [8-bit Access Register] Flag At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM5CNE 1: Operation enabled Timer initialization 0: Normal operation TM5LDE 1: Initialization TM5BR value is loaded into TM5BC. Timer output 5 is set to “L” level. Count clock source selection 000: IOCLK 001: IOCLK/8...
Page 214 Chapter 8 8-bit Timer Timer 6 Mode Register (TM6MD: 0x0000A1A4) [8-bit Access Register] Flag At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM6CNE 1: Operation enabled Timer initialization 0: Normal operation TM6LDE 1: Initialization TM6BR value is loaded into TM6BC. Count clock source selection 000: IOCLK 001: IOCLK/8...
Page 215 Chapter 8 8-bit Timer Timer 7 Mode Register (TM7MD: 0x0000A1A5) [8,16-bit Access Register] Flag At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM7CNE 1: Operation enabled Timer initialization 0: Normal operation TM7LDE 1: Initialization TM7BR value is loaded into TM7BC. Timer output 7 is set to “L” level. Count clock source selection 000: IOCLK 001: IOCLK/8...
Page 216 Chapter 8 8-bit Timer Timer 14 Mode Register (TM14MD: 0x0000A1C0) [8-bit Access Register] Flag TM14 TM14 TM14 TM14 TM14 At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM14CNE 1: Operation enabled Timer initialization 0: Normal operation TM14LDE 1: Initialization TM14BR value is loaded into TM14BC.
Page 217 Chapter 8 8-bit Timer Timer 15 Mode Register (TM15MD: 0x0000A1C1) [8-bit Access Register] Flag TM15 TM15 TM15 TM15 TM15 At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM15CNE 1: Operation enabled Timer initialization 0: Normal operation TM15LDE 1: Initialization TM15BR value is loaded into TM15BC.
Page 218 Chapter 8 8-bit Timer Timer 16 Mode Register (TM16MD: 0x0000A1C4) [8-bit Access Register] Flag TM16 TM16 TM16 TM16 TM16 At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM16CNE 1: Operation enabled Timer initialization 0: Normal operation TM16LDE 1: Initialization TM16BR value is loaded into TM16BC.
Page 219 Chapter 8 8-bit Timer Timer 17 Mode Register (TM17MD: 0x0000A1C5) [8-bit Access Register] Flag TM17 TM17 TM17 TM17 TM17 At reset Access Flag Description Set condition Timer operation enable 0: Operation disabled TM17CNE 1: Operation enabled Timer initialization 0: Normal operation 1: Initialization TM17LDE TM17BR value is loaded into TM17BC.
Page 220: Prescaler
Chapter 8 8-bit Timer 8.3 Prescaler 8.3.1 Prescaler Operation Prescaler Operation Prescaler outputs 1/8, 1/32, and 1/128 dividing clock with using IOCLK as an input clock. Count Clock Source and Prescaler When selecting IOCLK/8, IOCLK/32, or IOCLK/128 to count clock source of timer, the prescaler should be set up.
Page 221: Setup Example
Chapter 8 8-bit Timer 8.3.2 Setup Example Prescaler Setup Example Count clock source (IOCLK/32) which is output from the prescaler is selected to the count clock of the timer 0. A setup procedure with a description of each step is shown below: Setup Procedure Description (1) Stop the counter...
Page 222: Interval Timer
Chapter 8 8-bit Timer 8.4 Interval Timer 8.4.1 Interval Timer Operation Interval timer function is the function that can constantly generate interrupts at regular time intervals. Clock Source Selection The generation cycle of timer interrupts is set in advance by the clock source selection and the setting value of the base register (TMnBR).
Page 223 Chapter 8 8-bit Timer Setting a Timer Base Register Set the generation cycle of a timer interrupt to the base register TMnBR. Timer interrupt = (TMnBR setting + 1) × Count clock source cycle Count Timing of Timer Operation The binary counter counts down with the selected count source as a count clock. The basic operation of the whole function of 8-bit timer is as follows: Count clock TMnLDE flag...
Page 224 Chapter 8 8-bit Timer Count Timing When the Underflow of Timer is Selected to the Count Source Count clock Timer 0 base register Timer 0 01 00 01 00 01 00 N-1 N-2 binary counter Interrupt request TMIRQ0 Timer 1 base register Timer 1 binary counter...
Page 225: Setup Example
Chapter 8 8-bit Timer 8.4.2 Setup Example Interval Timer Setup Example Timer function can be set by using timer 0 that generates the constant interrupts. Interrupts are generated every 150 dividing (5µs) by selecting the clock source IOCLK. The oscillator frequency is set to 10 MHz, 6 multiplica- tion and IOCLK=MCLK/2.
Page 226: Timer Output Function
Chapter 8 8-bit Timer 8.5 Timer Output Function 8.5.1 Timer Output Function Operation TMnIO pin can output a pulse signal at any frequency. Timer Output Operation Signals of 2 times of the timer interrupt generation cycle can be output. Output pins are as follows: Table:8.5.1 Timer and Output Pin Timer 0 Timer 1 Timer 2...
Page 227: Setup Example
Chapter 8 8-bit Timer 8.5.2 Setup Example Timer Output Setup Example The TM1IO pin outputs 100 KHz pulse by using timer 1. In order to output 100 KHz, select IOCLK for a count clock source, and set 1/2 cycle (200 KHz) to the timer 1 base register. An example setup procedure, with a description of each step is shown below.
Page 228: Event Count
Chapter 8 8-bit Timer 8.6 Event Count 8.6.1 Operation Event count operation is to count the rising edge of the TMnIO pin input as count clock. Event Count Operation When the TMnIO pin is selected to the clock source, the event counter operates. The event count operation means that the binary counter (TMnBC) counts down the external signal input to the TMnIO pin.
Page 229: Setup Example
Chapter 8 8-bit Timer 8.6.2 Setup Example Event Count Setup Example If the rising edge of the TM1IO input pin is detected 5 times with the timer 1, an interrupt is generated. An exam- ple setup procedure, with a description of each step is shown below. Setup Procedure Description (1) Stop the counter...
Page 230: Cascade Connection
Chapter 8 8-bit Timer 8.7 Cascade Connection 8.7.1 Operation Cascading timers forms a 16-bit timer, 24-bit timer and 32-bit timer. Cascade Connection Operation (When using timers as a 16-bit timer) Table:8.7.1 shows timer functions at 16-bit timer cascade connection. Table:8.7.1 Cascade Connection Operation (When using timers as a 16-bit timer) 16-bit timer Timer 1 + timer Timer 2 + timer...
Page 231 Chapter 8 8-bit Timer Cascade Connection Operation (When using timers as a 24-bit timer) Table:8.7.2 shows timer functions at 24-bit timer cascade connection. Table:8.7.2 Cascade Connection Operation (When using timers as a 24-bit timer) 24-bit timer Timer 2 + timer 1 + timer Timer 3 + timer 2 + timer Timer 6 + timer 5 + timer Timer 7 + timer 6 + timer...
Page 232 Chapter 8 8-bit Timer Cascade Connection Operation (When using timers as a 32-bit timer) Table:8.7.3 shows timer functions at 32-bit timer cascade connection. Table:8.7.3 Cascade Connection Operation (When using timers as a 32-bit timer) 32-bit timer Timer 3 + timer 2 + timer 1 Timer 7 + timer 6 + timer 5 Timer 17 + timer 16 + timer 15 + timer 0...
Page 233 Chapter 8 8-bit Timer In reading out value of binary counter during timer operation with 8-bit timer in cascade con- nection, the value of binary counter may not be correctly read out. There are multiple binary counters of 8-bit timer, but all binary counters connectable in cas- cade are not allocated to continuous addresses.
Page 234 Chapter 8 8-bit Timer Selecting the Count Source Select any desired count source for the lowest-order timer. Set the count clock source for high-order timers ( except the lowest-order timer) to “cascading”. For example, when using timers 0 and 1 as a 16-bit timer, set a desired count clock source for timer 0 and the count clock source for timer 1 to “cascading”.
Page 235: Setup Example
Chapter 8 8-bit Timer 8.7.2 Setup Example Cascade Connection Setup Example Setting example of timer function that an interrupt is constantly generated by cascade connection of timer 0 and timer 1, as a 16-bit timer is shown. An interrupt is generated 30000 times every 1 ms by selecting clock source IOCLK.
Page 236 Chapter 8 8-bit Timer Setup Procedure Description (8) Start the timer operation (8) Set the TM1CNE flag of the TM1MD register to “1” to TM1MD(0x0000A181) operate the timer 1 of the upper timer. Set the TM0CNE bp7: TM1CNE=1 flag of the TM0MD register to “1” to operate the timer 0. TM0MD(0x0000A180) bp7: TM0CNE=1 TM1BC+TM0BC counter counts down as a 16-bit counter.
Page 237: Chapter 9 16-Bit Timer
IX.. Chapter 9 16-bit Timer...
Page 238: Overview
Chapter 9 16-bit Timer 9.1 Overview This LSI contains 6 general-purpose 16-bit timers (Timer 8, timer 9, timer 10, timer 11, timer 12, and timer 13). 9.1.1 Functions Table: 9.19. shows the function of each timer. Table:9.1.1 16-bit Timer Functions Timer 8 Timer 9 Timer 10...
Page 239: Connection
Chapter 9 16-bit Timer 9.1.2 Connection 16-bit Timer Connection Diagram (TImer 8, timer 9) Prescaler TM8PSC IOCLK Prescaler control register TMIN0 Timer 8 overflow/underflow interrupt NTMHIRQ TMIN1 NTMHAIRQ Timer 8 compare/capture A interrupt TM2IRQ TMIN2 Timer 8 Timer 8 compare/capture B interrupt NTMHBIRQ TMIN3 TM8AIO...
Page 240 Chapter 9 16-bit Timer 16-bit Timer Connection Diagram (TImer 10, 11) Prescaler TM10PSC IOCLK Prescaler control register TMIN0 NTMHIRQ Timer 10 overflow/underflow interrupt TMIN1 Timer 10 compare/capture A interrupt NTMHAIRQ TMIN2 TM0IRQ Timer 10 Timer 10 compare/capture B interrupt NTMHBIRQ TM1IRQ TMIN3 TM10AIO...
Page 241 Chapter 9 16-bit Timer 16-bit Timer Connection Diagram (TImer 12, 13) IOCLK Prescaler TM12PSC MCLK Prescaler control register TM12CLKSEL TMIN0 Timer 12 overflow / underflow interrupt NTMHIRQ TMIN1 NTMHAIRQ Timer 12 compare/capture A interrupt TMIN2 TM6IRQ Timer 12 NTMHBIRQ Timer 12 compare/capture B interrupt TM7IRQ TMIN3 TMAOUT...
Page 242: Block Diagram
Chapter 9 16-bit Timer 9.1.3 Block Diagram 16-bit TImer Block Diagram Timer Count source TMIN0 TMIN1 TMIN2 TMBC NTMHIRQ Count Binary counter TMIN3 Overflow/underflow interrupt control Pin output TMAOUT output TMBOUT control Event count two-phase encoding Capture Match NTMAIRQ Pin input Compare/capture A interrupt TMAIN TMCA...
Page 243: Registers
Chapter 9 16-bit Timer 9.2 Control registers Timer 8 to timer 13 are composed of the prescaler control register (TMnPSC), the binary counter (TMnBC), com- pare/capture A register (TMnCA) and compare/capture B register (TMnCB), and are controlled by the mode reg- ister (TMnMD), compare/capture A mode register (TMnMDA) and compare/capture B mode register (TMnMDB).
Page 244 Chapter 9 16-bit Timer Register Address Access size Description Page TM10PSC 0x0000A254 8,16 Timer 10 prescaler control register IX-10 TM10CA 0x0000A248 Timer 10 compare/capture A register IX-17 TM10CB 0x0000A24C Timer 10 compare/capture B register IX-18 TM10BC 0x0000A250 Timer 10 binary counter IX-14 TM10MD 0x0000A240...
Page 245: Prescaler Control Registers
Chapter 9 16-bit Timer 9.2.2 Prescaler Control Registers These registers need to be controlled when the prescaler output is selected to the count clock source of the16-bit timer. Timer 8 Prescaler Control Register (TM8PSC: 0x0000A214) [8, 16-bit Access Register] Flag PSCNE At rest Access...
Page 246 Chapter 9 16-bit Timer Timer 10 Prescaler Control Register (TM10PSC: 0x0000A254) [8, 16-bit Access Register] Flag PSCNE At reset Access Flag Description Setting condition Prescaler operation enable 0: Operation disabled TMPSCNE 1: Operation enabled Timer 11 Prescaler Control Register (TM11PSC: 0x0000A274) [8, 16-bit Access Register] Flag PSCNE At reset...
Page 247 Chapter 9 16-bit Timer Timer 13 Prescaler Control Register (TM13PSC: 0x0000A2B4) [8, 16-bit Access Register] Flag PSCNE At reset Access Flag Description Setting condition Prescaler operation enable 0: Operation disabled TMPSCNE 1: Operation enabled External Prescaler Control Register 1 (TMEXPSC16: 0x0000A218) [8, 16-bit Access Register] Flag PSCNE At reset...
Page 248 Chapter 9 16-bit Timer Timer 12 Clock Source Selection Register (TM12CLKSEL: 0x0000A298) [8, 16-bit Access Register] Flag 12CLK At reset Access Flag Description Setting condition Clock source selection 0: IOCLK TM12CLK 1: MCLK Timer 13 Clock Source Selection Register (TM13CLKSEL: 0x0000A2B8)[8, 16-bit Access Register] Flag 13CLK At reset...
Page 249: Programmable Timer Registers
Chapter 9 16-bit Timer 9.2.3 Programmable Timer Registers Timer 8 to timer 11 each have 16-bit programmable timer registers. Programmable timer registers are composed of the binary counter (TMnBC), the compare/capture A register (TMnCA) and the compare/capture B register (TMnCB). Timer 8 Binary Counter (TM8BC: 0x0000A210) [16-bit Access Register] Flag BC15...
Page 250 Chapter 9 16-bit Timer Timer 9 Binary Counter (TM9BC: 0x0000A230) [16-bit Access Register] Flag BC15 BC14 BC13 BC12 BC11 BC10 At reset Access Timer 10 Binary Counter (TM10BC: 0x0000A250) [16-bit Access Register] Flag BC15 BC14 BC13 BC12 BC11 BC10 At reset Access Timer 11 Binary Counter (TM11BC: 0x0000A270) [16-bit Access Register] Flag...
Page 251 Chapter 9 16-bit Timer Timer 8 Compare/Capture A Register (TM8CA: 0x0000A208) [16-bit Access Register] Flag CA15 CA14 CA13 CA12 CA11 CA10 At reset Access This is a register which has compare operation and capture operation. For the appropriate use of both operations, this register is set by the TMAM1-0 flag of the timer compare capture A(B) register.
Page 252 Chapter 9 16-bit Timer Table:9.2.3 Updated Timing of Compare/Capture Register (At Double Buffer) TMLCE flag (TMnMD)=0 TMLCE flag (TMnMD)=1 When initializing a timer (when the TMnCA←TMnCBUFF *1 TMnCA←TMnCBUFF TMLDE flag of the TMnMD register is set TMnCB←TMnCBUFF TMnCB←TMnCBUFF to “1”) Count clock up (down) TMnBC overflow TMnCA←TMnCBUFF...
Page 253 Chapter 9 16-bit Timer Timer 9 Compare/Capture A Register (TM9CA: 0x0000A228) [16-bit Access Register] Flag CA15 CA14 CA13 CA12 CA11 CA10 At reset Access Timer 10 Compare/Capture A Register (TM10CA: 0x0000A248) [16-bit Access Register] Flag CA15 CA14 CA13 CA12 CA11 CA10 At reset Access...
Page 254 Chapter 9 16-bit Timer Timer 8 Compare/Capture B Register (TM8CB: 0x0000A20C) [16-bit Access Register] Flag CB15 CB14 CB13 CB12 CB11 CB10 At reset Access Timer 9 Compare/Capture B Register (TM9CB: 0x0000A22C) [16-bit Access Register] Flag CB15 CB14 CB13 CB12 CB11 CB10 At reset Access...
Page 255: Timer Mode Registers
Chapter 9 16-bit Timer 9.2.4 Timer Mode Registers These are readable/writable registers which control the timer 8 to timer 13. The timer compare/capture A mode register controls the compare/capture A register, and the timer compare/capture B mode register controls the com- pare/capture B register.
Page 256 Chapter 9 16-bit Timer Timer 8 Mode Register (TM8MD: 0x0000A200) [8, 16-bit Access Register] Flag At reset Access Flag Description Setting condition Timer operation display 0: Timer stopped TMXF 1: Timer operating Timer external trigger enable 0: Timer activation disabled by external trigger. (trigger input ignored) 1: Timer start when the falling edge is input TMTGE (when timer A pin polarity selection bit is “0”)
Page 257 Chapter 9 16-bit Timer Timer 9 Mode Register (TM9MD: 0x0000A220) [8, 16-bit Access Register] Flag At reset Access Flag Description Setting condition Timer operation display 0: Timer stopped TMXF 1: Timer operating Timer external trigger enable 0: Timer activation disabled by external trigger. (trigger input ignored) 1: Timer start when the falling edge is input TMTGE (when timer A pin polarity selection bit is “0”)
Page 258 Chapter 9 16-bit Timer Timer 10 Mode Register (TM10MD: 0x0000A240) [8, 16-bit Access Register] Flag At reset Access Flag Description Setting condition Timer operation display 0: Timer stopping TMXF 1: Timer operating Timer external trigger enable 0: Timer activation disabled by external trigger. (trigger input ignored) 1: Timer start when the falling edge is input TMTGE (when timer A pin polarity selection bit is “0”)
Page 259 Chapter 9 16-bit Timer Timer 11 Mode Register (TM11MD: 0x0000A260) [8, 16-bit Access Register] Flag At reset Access Flag Description Setting condition Timer operation display 0: Timer stopping TMXF 1: Timer operating Timer external trigger enable 0: Timer activation disabled by external trigger (trigger input ignored) 1: Timer start when the falling edge is input TMTGE (when timer A pin polarity selection bit is “0”)
Page 260 Chapter 9 16-bit Timer Timer 12 Mode Register (TM12MD: 0x0000A280) [8, 16-bit Access Register] Flag At reset Access Flag Description Setting condition Timer operation display 0: Timer stopping TMXF 1: Timer operating Timer external trigger enable 0:Timer activation disabled by PWM0 1: Timer activation enabled by PWM0 TMTGE When timer activation is enable by PWM0, set the activation trigger...
Page 261 Chapter 9 16-bit Timer Timer 13 Mode Register (TM13MD: 0x0000A2A0) [8, 16-bit Access Register] Flag At reset Access Flag Description Setting condition Timer operation display 0: Timer stopping TMXF 1: Timer operating Timer external trigger enable 0:Timer activation disabled by PWM1 1: Timer activation enabled by PWM1 TMTGE When timer activation is enable by PWM1, set the activation trigger...
Page 262 Chapter 9 16-bit Timer Timer 8 Compare/Capture A Mode Register (TM8MDA: 0x0000A204) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare/capture A operation 00: Compare register (double buffer) mode selection 01: Compare register (single buffer) TMAM1 10: Capture register ( single-edge operation) TMAM0 Capture at the edge selected by timer A pin polarity selection bit.
Page 263 Chapter 9 16-bit Timer Timer 9 Compare/Capture A Mode Register (TM9MDA: 0x0000A224) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare/capture A operation 00: Compare register (double buffer) mode selection 01: Compare register (single buffer) TMAM1 10: Capture register ( single-edge operation) TMAM0 Capture at the edge selected by timer A pin polarity selection bit.
Page 264 Chapter 9 16-bit Timer Timer 10 Compare/Capture A Mode Register (TM10MDA: 0x0000A0244) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare/capture A operation 00: Compare register (double buffer) mode selection 01: Compare register (single buffer) TMAM1 10: Capture register ( single-edge operation) TMAM0 Capture at the edge selected by timer A pin polarity selection bit.
Page 265 Chapter 9 16-bit Timer Timer 11 Compare/Capture A Mode Register (TM11MDA: 0x0000A264) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare/capture A operation 00: Compare register (double buffer) mode selection 01: Compare register (single buffer) TMAM1 10: Capture register ( single-edge operation) TMAM0 Capture at the edge selected by timer A pin polarity selection bit.
Page 266 Chapter 9 16-bit Timer Timer 12 Compare A Mode Register (TM12MDA: 0x0000A284) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare A operation mode selec- 00: Compare register (double buffer) TMAM1 tion 01: Compare register (single buffer) TMAM0 10: Setting prohibited 11: Setting prohibited...
Page 267 Chapter 9 16-bit Timer Timer 13 Compare A Mode Register (TM13MDA: 0x0000A2A4) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare A operation mode selec- 00: Compare register (double buffer) TMAM1 tion 01: Compare register (single buffer) TMAM0 10: Setting prohibited 11: Setting prohibited...
Page 268 Chapter 9 16-bit Timer Timer 8 Compare/Capture B Mode Register (TM8MDB: 0x0000A205) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare/capture B operation 00: Compare register (double buffer) mode selection 01: Compare register (single buffer) TMBM1 10: Capture register ( single-edge operation) TMBM0 Capture at the edge selected by timer B pin polarity selection bit.
Page 269 Chapter 9 16-bit Timer Timer 9 Compare/Capture B Mode Register (TM9MDB: 0x0000A225) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare/capture B operation 00: Compare register (double buffer) mode selection 01: Compare register (single buffer) TMBM1 10: Capture register ( single-edge operation) TMBM0 Capture at the edge selected by timer B pin polarity selection bit.
Page 270 Chapter 9 16-bit Timer Timer 10 Compare/Capture B Mode Register (TM10MDB: 0x0000A245) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare/capture B operation 00: Compare register (double buffer) mode selection 01: Compare register (single buffer) TMBM1 10: Capture register ( single-edge operation) TMBM0 Capture at the edge selected by timer B pin polarity selection bit.
Page 271 Chapter 9 16-bit Timer Timer 11 Compare/Capture B Mode Register (TM11MDB: 0x0000A265) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare/capture B operation 00: Compare register (double buffer) mode selection 01: Compare register (single buffer) TMBM1 10: Capture register ( single-edge operation) TMBM0 Capture at the edge selected by timer B pin polarity selection bit.
Page 272 Chapter 9 16-bit Timer Timer 12 Compare B Mode Register (TM12MDB: 0x0000A285) [8-bit Access Register] Flag At reset Access Flag Description Setting condition Timer compare B operation mode selec- 00: Compare register (double buffer) TMBM1 tion 01: Compare register (single buffer) TMBM0 10: Setting prohibited 11: Setting prohibited...
Page 273: Prescaler
Chapter 9 16-bit Timer 9.3 Prescaler 9.3.1 Prescaler Operation Prescaler operation Prescaler outputs IOCLK/8 and IOCLK/64 with using IOCLK as an input clock and MCLK/8 with using MCLK as an input clock. Count Source and Prescaler When IOCLK/8, IOCLK/64 or MCLK/8 is selected as a timer count source, the setting of the prescaler is neces- sary.
Page 274: Setup Example
Chapter 9 16-bit Timer 9.3.2 Setup Example Setup Example Timer function can be set by using timer 8 that generates the constant interrupts. Interrupts are generated every 1 ms by selecting the clock source IOCLK/8 and using the prescaler function. The oscillator frequency is set to 10 MHz, 6 multiplication and IOCLK=MCLK/2.
Page 275: Interval Timer
Chapter 9 16-bit Timer Interval Timer 9.4.1 Interval Timer Function Operation Interval timer function is the function which can generate the interrupts repeatedly at regular time intervals. Clock Source Selection The generation cycle of timer interrupts is set in advance by the clock source selection and the setting value of the base register (TMnBR).
Page 276 Chapter 9 16-bit Timer Count Timing of Timer Operation The binary counter counts up with the selected count source as a count clock. Table: 9.4.2 shows operation condi- tion and Figure: 9.4.1 shows count timing. Table:9.4.2 Operation Condition Operation condition Setting description Timer up or down selection Up count...
Page 277: Setup Example
Chapter 9 16-bit Timer 9.4.2 Setup Example Interval Timer Setup Example Timer function can be set by using timer 8 that generates the constant interrupts. Interrupts are generated every 1 ms by selecting the clock source IOCLK. The oscillator frequency is set to 10 MHz, 6 multiplication and IOCLK=MCLK/2.
Page 278 Chapter 9 16-bit Timer Setup Procedure Description (11) Start the timer operation (11) Set the TMCNE flag of the TM8MD register to “1” to TM8MD(0x0000A200) operate the timer 8. bp7: TMCNE=1 TM8BC counter starts to count up. When the TM8BC counter and the TM8CA match, the timer 8 compare/cap- ture A interrupt is generated at the rising edge of the next count clock.
Page 279: Event Count
Chapter 9 16-bit Timer 9.5 Event Count 9.5.1 Event Count Operation Event count operation is to count the edge selected by the TMnBIN pin as a count clock. Also, it can mask (stop counting) the count clock by the TMnAIN pin. Event Count Operation When the TMnBIN pin is selected to a clock source, the event counter operates.
Page 280 Chapter 9 16-bit Timer Count Timing of Event Count Operation TMnBIN pin input is sampled by IOCLK. The edge selected by the TMnBIN pin input is counted, and the binary counter counts up. The pulse width should be IOCLK × 1.5 or more for detecting the edge. Table: 9.5.4 shows operation condition and Figure: 9.5.1 the count timing.
Page 281 Chapter 9 16-bit Timer Count Timing of Count Control Input Count timing of count control input is shown below. The TMAEG flag is set to “0”. When the TMnAIN pin is set to “L”, counting up stops. Count clock Input pin (TMnAIN) Binary counter 0001...
Page 282: Setup Example
Chapter 9 16-bit Timer 9.5.2 Setup Example Event Count Setup Example If the rising edge of the TM8BIO input pin is detected 5 times with the timer 8, an interrupt is generated. An example setup procedure, with a description of each step is shown below. Setup Procedure Description (1) Stop the counter...
Page 283 Chapter 9 16-bit Timer Setup Procedure Description (11) Enable the interrupt (11) Set the G7IEO flag of the G7ICR register to “1” to G7ICR(0x0000891C) enable the interrupt. bp8: G7IE1=1 (12) Start the timer operation (12) Set the TMCNE flag of the TM8MD register to “1” to TM8MD(0x0000A200) operate the timer 8.
Page 284: Up/Down Counting
Chapter 9 16-bit Timer 9.6 Up/Down Counting 9.6.1 Up/Down Counting Operation Up/down counting is the function that the binary counter counts up or down according to the condition of the input pin. Input Pin Table: 9.6.1 shows the pins for up/down counting. Table:9.6.1 Timer and Up/Down Counting Input Pin Timer 8 Timer 9...
Page 285 Chapter 9 16-bit Timer Setting Up/Down Counting (1-fold, 2-phase encoding) Select “1-fold and 2-phase encoding” by the timer count clock source selection of the timer mode register (TMnMD). The binary counter counts up at the rising edge of the TMnBIN pin when the TMnAIN pin is set to “1”...
Page 286 Chapter 9 16-bit Timer Count TIming of Up/Down Counting It is indicated that the count timing goes up or down according to the input pin (TMnAIN pin) at the timing of the count clock. Count clock TMnAIN Binary counter 0016 0017 0018 0017 0016...
Page 287: Setup Example
Chapter 9 16-bit Timer 9.6.2 Setup Example Up/Down Counting Setup Example The binary counter counts up when the external input signal(TM8AIO) is “H” and counts down when it is “L” at timing of the timer 8 count clock. The count clock is IOCLK, and the oscillator frequency is set to 10 MHz, 6 multiplication and IOCLK=MCLK/2.
Page 288: Timer Output
Chapter 9 16-bit Timer 9.7 Timer Output 9.7.1 Timer Output Operation Timer output is the function which inverts output levels of pins every regular cycles. Output Pin Table; 9.7.1 shows timer output pins. Table:9.7.1 Timer and Timer Output Pin Timer 8 TImer 9 Timer 10 Timer 11...
Page 289 Chapter 9 16-bit Timer Setting Timer Output Select “timer output” by the timer output waveform selection flag of the timer compare/capture mode register. Timer pin polarity selection is the flag which sets the initial value of pin output. When it is set to “0”, the initial value is “L”...
Page 290 Chapter 9 16-bit Timer Count TIming of Timer Output Counting up starts from matching condition of the binary counter and the compare/capture register, the output pin is inverted to operate timer output. Table; 9.7.4 shows the preconditions for count timing of timer output and Fig- ure;...
Page 291: Setup Example
Chapter 9 16-bit Timer 9.7.2 Setup Example TImer Output Setup Example The output pin (TM8AIO) using timer 8 outputs waveforms as shown below (repeating “L” output for 1ms and “H” output for the next 1ms). IOCLK is selected as clock source to match the binary counter and the compare/ capture register for every 1 ms.
Page 292 Chapter 9 16-bit Timer Setup Procedure Description (9) Initialize the timer 8 (9) Set the TMLDE flag of the TM8MD register to “1” to TM8MD(0x0000A200) initialize the timer 8. The value of the compare register bp6: TMLDE=1 buffer is loaded into the TM8CA register. Reset the TMLDE flag to “0”...
Page 293: Pwm Output
Chapter 9 16-bit Timer 9.8 PWM Output 9.8.1 PWM Output Operation PWM output is the function that pins output the standard PWM output, which is determined by the overflow tim- ing of the binary counter and match timing of the timer binary counter and the compare register. Output Pin Table: 9.8.1 shows PWM output pins.
Page 294 Chapter 9 16-bit Timer Setting PWM Output Select the timer output waveform selection flag of the timer compare/capture mode register. When TM8AIO, TM9AIO, TM10AIO, TM11IO0 and TM11IO1 pins are used, Set when TMnBC and TMnCA match, and reset when TMnBC and TMnCB match. Set when TMnBC and TMnCA match, and reset when TMnBC overflows.
Page 295 Chapter 9 16-bit Timer Count Timing of PWM Output (1) The polarity for output pins changes by matching of the binary counter and the compare/capture A register and matching of the binary counter and the compare/capture B register. Table 9.8.4 shows the preconditions for PWM output count timing, and Figure;...
Page 296 Chapter 9 16-bit Timer Count Timing of PWM Output (2) The output pin polarity changes by matching of the binary counter and the compare/capture A register and the overflow of the binary counter. Table; 9.8.5 shows the preconditions for count timing of PWM output, and Figure; 9.8.2 shows count timing.
Page 297: Setup Example
Chapter 9 16-bit Timer 9.8.2 Setup Example PWM Output Setup Example The output pin (TM8AIO) using timer 8 outputs waveforms as shown below (repeating “L” output for 1.5 ms and “H” output for the next 0.5 ms). IOCLK is selected as clock source to match the binary counter and the compare/ capture B register for every 1.5 ms and to match the binary counter and the compare/capture A register for every 2 ms.
Page 298 Chapter 9 16-bit Timer Setup Procedure Description (8) Select the timer B pin polarity (8) Set the TMBEG flag of the TM8MDB register to “0” to set TM8MDB(0x0000A205) the initial condition of pin output to “L”. Set it to “1” bp5: TMBEG=0 when the initial condition of the pin output is set to “H”.
Page 299: Input Capture
Chapter 9 16-bit Timer 9.9 Input Capture 9.9.1 Input Capture Operation Input capture function reads the value of the binary counter into the compare/capture register at the trigger set by the external input signal (both edge, rising edge, falling edge). Setting Input Capture Set the TMACE flag of the timer compare/capture mode register to “1”...
Page 300: Setup Example
Chapter 9 16-bit Timer Count clock Capture input edge Edge detection flag Binary counter Compare/capture register Interrupt request flag Figure:9.9.1 Count TIming of Input Capture 9.9.2 Setup Example Input Capture Setup Example The value of the binary counter is read at the rising edge of the external input signal (TM8AIO), and the pulse width can be measured.
Page 301 Chapter 9 16-bit Timer Setup Procedure Description (5) Set the timer counter clear enabled (5) Set the TMCLE flag of the TM8MD register to “1” to TM8MD(0x0000A200) enable the clear operation of the TM8BC counter. bp11: TMCLE=1 When the value of the TM8BC is captured to the TM8CA register, the TM8BC counter is cleared.
Page 302: 1-Shot Output
Chapter 9 16-bit Timer 9.10 1-Shot Output 9.10.1 1-Shot Output Operation 1-shot output is to count only one time at a certain period of time. Setting One Shot Output 1-shot operation is set by setting the TM0NE flag of the timer mode register (TMnMD) to “1”. 1-shot operation stops the timer by matching the binary counter and the timer compare/capture A register Count Timing of One Shot Output (TMCLE flag= 0) The binary counter stops at the next count clock after the value of the binary counter matches the value of the...
Page 303: Setup Example
Chapter 9 16-bit Timer 9.10.2 Setup Example 1-Shot Output Setup Example As taking an example of the timer 8, it is explained that timers can operate 1 ms one time. Select IOCLK as clock source to match the binary counter and the compare/capture register after 1ms . The oscillation frequency is 10 MHz, 6 multiplication and IOCLK=MCLK/2.
Page 304: External Trigger
Chapter 9 16-bit Timer 9.11 External Trigger 9.11.1 External Trigger Operation External trigger is to activate timers by external input pins. Setting External Trigger Operation Timers can be activated with the external trigger by setting the TMTGE flag of the timer mode register (TMnMD) to “1”.
Page 305 Chapter 9 16-bit Timer Count Timing of External Trigger (TMCLE flag= 0) When the TMCLE flag is set to “0” and the binary counter stops at the rising edge of the next count clock of matching the binary counter and the compare/capture register, the binary counter is the setting value of the com- pare/capture register + 1.
Page 306: Setup Example
Chapter 9 16-bit Timer 9.11.2 Setup Example External Trigger Setup Example Timer 8 can be activated at the rising edge of the external input pin (TM8AIO) . The count clock operates in 1 ms with selecting IOCLK. After 1 ms operation, the count clock stops timer operation and operates for 1 ms again at the rising edge of the external input pin as well.
Page 307 Chapter 9 16-bit Timer Setup Procedure Description (10) Set the output pin (I/O function) (10) Set the P36D flag of the port 3 I/O control register P3DIR(0x0000A023) (P3MD) to “0” to set the I/O control to the input pin. bp0: P36D=0 (11) Initialize the timer 8 (11) Set the TMLDE flag of the TM8MD register to “1”...
Page 308: A/D Converter Start
Chapter 9 16-bit Timer 9.12 A/D Converter Start 9.12.1 Operation A/D converter can be started using the interrupts of the timer 12 and timer 13. Table:9.12.1 Interrupt Factors which Can Start A/D Converter Factor Timer 12 compare/capture A interrupt Timer 12 compare/capture B interrupt Timer 13 compare/capture A interrupt Timer 13 compare/capture B interrupt Timer 12 compare/capture A interrupt...
Page 309: Chapter 10 Motor Control Pwm
Chapter 10 Motor Control PWM...
Page 310: Overview
Chapter 10 Motor Control PWM 10.1 Overview This LSI incorporates 2 complementary 3-phase PWM (PWM0, PWM1) for motor control applications. 10.1.1 Functions Table:10.1.1 Functions PWM for Motor Control PWM0 PWM1 Page Interrupt cause PWM0UFIRQ, PWM0CPIRQ PWM1UFIRQ,PWM1CPIRQ 3-phase PWM U-phase, V-phase, W-phase U-phase, V-phase, W-phase Waveform mode Triangular wave, Saw-tooth wave...
Page 311: Block Diagram
Chapter 10 Motor Control PWM 10.1.2 Block Diagram Motor Control PWM Block Diagram Counting start PWM mode control Output timing PWM period buffer control buffer PWMMDn Deadtimer enable/disable PWMSETn PWMDCNTn Double buffer selection PWM period Output timing period Output polarity control buffer Output switching control buffer PWMDCNTn PWMSETn...
Page 312: Control Registers
Chapter 10 Motor Control PWM 10.2 Control Registers 10.2.1 Control Registers for Motor Control PWM Table: 10.2.1 shows registers which control PWM for motor control applications. Table:10.2.1 Control Registers for Motor Control PWM Register Address Access size Description Page PWMMD0 0x0000A300 8,16 PWM0 mode control register...
Page 313: Pwm Mode Control Registers
Chapter 10 Motor Control PWM 10.2.2 PWM Mode Control Registers PWM mode control registers are used to set various modes for the motor control block. PWM0 Mode Control Register (PWMMD0: 0x0000A300) [8,16-bit Access Register] Flag INTA INTB At reset Access Flag Description Setting condition...
Page 314 Chapter 10 Motor Control PWM PWM1 Mode Control Register (PWMMD1: 0x0000A330) [8,16-bit Access Register] Flag INTA INTB At reset Access Flag Description Setting condition Simultaneous starting function of PWM0 0: Disabled SYNEN1 and PWM1 enable 1: Enabled Output timing varying function enable 0: Disabled SFTEN1 1: Enabled...
Page 315: Pwm Output Polarity Control Registers
Chapter 10 Motor Control PWM 10.2.3 PWM Output Polarity Control Registers PWM output polarity control register selects polarity for each of the PWM outputs. This register can select double-buffer or single-buffer mode by the SDSELAn flag of the PWM mode control reg- ister (PWMMDn).
Page 316 Chapter 10 Motor Control PWM PWM1 Output Polarity Control Register (OUTMD1: 0x0000A334) [8,16-bit Access Register] Flag At reset Access Flag Description Setting condition 15-6 Output polarity for NPWM12 0: Positive phase PXDTNW1 1: Negative phase Output polarity for PWM12 0: Positive phase PXDTW1 1: Negative phase Output polarity for NPWM11...
Page 317: Pwm Output Control Registers
Chapter 10 Motor Control PWM 10.2.4 PWM Output Control Registers PWM output control register is used to switch between 2 output sources, PWM output or H/L level output. This register can select double-buffer or single-buffer mode by the SDSELBn flag of the PWM mode control reg- ister (PWMMDn).
Page 318 Chapter 10 Motor Control PWM PWM1 Output Control Register (PWMSEL1: 0x0000A338) [8,16-bit Access Register] Flag PSEL PSEL PSEL PSEL PSEL PSEL OTLV OTLV OTLV OTLV OTLV OTLV At reset Access Flag Description Setting condition 15-12 NPWM12 output sources 0: PWM output PSELN12 1: H/L level output PWM12 output sources...
Page 319: Pwm Period Setting Registers
Chapter 10 Motor Control PWM 10.2.5 PWM Period Setting Registers PWM period setting register is used to determine the period for 3-phase of PWM0 and PWM1. This register needs to be set only when double-buffer mode is selected. The value of PWMSETn is loaded into the register at the timing selected with the PWM mode control register (PWMMDn).
Page 320: Pwm Phase Value To Be Compared Setting Registers
Chapter 10 Motor Control PWM 10.2.6 PWM Phase Value to be Compared Setting Registers PWM phase value to be compared setting register is used to determine the timing at which 3-phase output of PWM0 and PWM1 is to change. This register needs to be set only when double-buffer mode is selected. The value of TCMPn is loaded into the register at the timing selected with the PWM mode control register (PWM- MDn).
Page 321 Chapter 10 Motor Control PWM PWM10 Phase Value to be Compared Setting Register (TCMP1A: 0x0000A340) [16-bit Access Register] Flag At reset Access Flag Description Setting condition TCPA1F Timing at which PWM10 phase output is Setting a value of PWM10 phase to be compared with the PWM1 15-0 to change setting binary counter...
Page 322: Dead Time Setting Registers
Chapter 10 Motor Control PWM 10.2.7 Dead Time Setting Registers Dead Time setting register is used to set dead time of PWM0 and PWM1. Dead Time is designed to insert on time delay into each of the upper and lower phases when the signal is inverted at PWM output. The dead time counter functions in synchronization with clock set by the PWM mode control register ‘PWMMDn) and counts 1 every 2 clock cycles.
Page 323: Output Timing Control Registers
Chapter 10 Motor Control PWM 10.2.8 Output Timing Control Registers Output timing control register is used to control the timing of PWM pin output. Output timing variable function is a function for pin output at any timing in 1 cycle of PWM. This register needs to be set only when double-buffer mode is selected.
Page 324: Bc Value Read Registers
Chapter 10 Motor Control PWM 10.2.9 BC Value Read Registers BC value read register is used to read the binary counter value of PWM0 and PWM1. PWM0 BC Value Read Register (PWMBC0: 0x0000A320) [16-bit Access Register] Flag At reset Access Flag Description Setting condition...
Page 325: Bc Status Read Registers
Chapter 10 Motor Control PWM 10.2.10 BC Status Read Registers BC status read register is used to read the binary counter’s counting status of PWM0 and PWM1. PWM0 BC Status Read Register (BCSTR0: 0x0000A324) [8,16-bit Access Register] Flag At reset Access Flag Description...
Page 326: Pwm Pin Protection Control Registers
Chapter 10 Motor Control PWM 10.2.11 PWM Pin Protection Control Registers This register is used to automatically bring the PWM output pins into high impedance state by the specified inter- rupt generation. The output pins can return from high impedance state by clearing the interrupt request flag (IR). This register needs to be set only when single-buffer mode is selected.
Page 327: Operation
Chapter 10 Motor Control PWM 10.3 Operation 10.3.1 Motor Control PWM Operation Waveform Mode Waveform mode can be set by the WAVEMDn flag of the PWM mode control register (PWMMDn). When “0” is set, triangular waves are specified and “1” is set, saw-tooth waves are specified. Table: 10.3.1 shows the output waveform logic operation formula and output level.
Page 328 Chapter 10 Motor Control PWM Setting PWM Period The 3-phase period for PWMn is set by the PWM period setting register (PWMSETn). PWM counting is operated by the PWMn binary counter (PWMBCn). The formula of the PWM period is as follows. The count clock of the PWMBCn counter is IOCLK.
Page 329 Chapter 10 Motor Control PWM Output Waveform Polarity The PWM output polarity control register (OUTMDn) can be used to control polarity of PWM output waveform. Table:10.3.3 shows the flags and set values. When the PXDTn0 flag is set to “1”, PWMn0 and NPWMn0 outputs are switched.
Page 330 Chapter 10 Motor Control PWM Double Buffer Each of the PWM registers is double-buffered to allow data changes during PWM operation. Registers read from and written to by the microcontroller are independent of registers referenced by the PWM. This makes it possible for microcontroller’s register values to be loaded into PWM’s registers in synchronization with PWM period.
Page 331 Chapter 10 Motor Control PWM Double Buffer Load Timing Double buffer load can be enabled by the PCRAEN flag and PCRBEN flag of the PWMMDn register. Table: 10.3.5 shows the relationship between the double buffer load timing and enable setting flag. Table:10.3.5 Double Buffer Load Timing and Enable Setting Flag Load timing Flag (Register)
Page 332 Chapter 10 Motor Control PWM Dead Time Dead Time is designed to insert on time delay into each of the upper and lower phases when the signal is inverted at each PWM output phase. The DTEN flag of the PWMMDn register is used to select whether to enable or dis- able dead time.
Page 333 Chapter 10 Motor Control PWM Setting H/L Level Output PWM output or H/L level output can be selected for each of the 6 PWM pins by the PSELNn2-0 flags and the PSELn2-0 flags of the PWM output control register (PWMSELn). L level output or H level output can be selected by the OUTVNn2-0 and OUTVn2- 0 when setting H/L level output.
Page 334 Chapter 10 Motor Control PWM Inserting Dead Time at H/L Level Output Dead Time is inserted as delay time when signals are switched. Therefore, dead time is inserted even when PWM output is switched over to H/L level output. The timing of dead time insertion is shown below. ORMDn = 0 PWM basic waveform...
Page 335 Chapter 10 Motor Control PWM Setting PWM Output Timing PWM output timing can be shifted by the PWM output timing control register (PWMDCNT) within PWM period. Set the SETENn flag of the PWMMDn register to “1” to valid shift function of PWM output timing. The relationship between the register value and PWM output timing is shown below.
Page 336 Chapter 10 Motor Control PWM X - 28 Operation...
Page 337: Chapter 11 Watchdog Timer
XI.. Chapter 11 Watchdog Timer...
Page 338: Overview
Chapter 11 Watchdog Timer 11.1 Overview This LSI has an internal 24-bit binary counter that can be used as a 16- to 24-bit watchdog timer. A watchdog timer overflow can generate a non-maskable interrupt. And if an overflow occurs for the second time in a row without clearing the binary counter of the watchdog timer, it is judged unable to return by software.
Page 339: Block Diagram
Chapter 11 Watchdog Timer 11.1.2 Block Diagram Watchdog Timer Block Diagram Internal reset signal Internal reset RSTCTR register generation SYSCLK Binary counter NRST Oscillation stabilization wait release Reset interrupt 8-bit binary counter WD0VFIRQ WDBC Reset Reset OSCI Control register Clock source 16-bit binary counter WDCTR selection...
Page 340: Control Registers
Chapter 11 Watchdog Timer 11.2 Control Registers Watchdog Timer is composed of the watchdog binary counter (WDBC), watchdog timer control register (WDCTR) and reset control register (RSTCTR). 11.2.1 Watchdog Timer Control Registers Table: 11.2.1 shows registers which control watchdog timers. Table:11.2.1 Watchdog Timer Control Registers Register Address...
Page 341: Watchdog Timer Control Register
Chapter 11 Watchdog Timer 11.2.3 Watchdog Timer Control Register The watchdog timer control register (WDCTR) is used to control the watchdog timer. Watchdog Timer Control Register (WDCTR: 0x00008202) [8,16-bit Access Register] Flag At reset Access Flag Description Setting condition Watchdog timer operation enable 0: Operation disabled (The oscillation stabilization wait operation is WDCNE possible)
Page 342: Reset Control Register
Chapter 11 Watchdog Timer 11.2.4 Reset Control Register Reset control register is used to generate a self-reset (internal reset). Reset Control Register (RSTCTR: 0x00008204) [8,16-bit Access Register] Flag CHIP At reset Access Flag Description Setting condition Self-reset (internal reset) A self-reset is generated when this flag is overwritten from “0” to “1”. A self-reset is not generated if this flag is set to “1”...
Page 343: Operation
Chapter 11 Watchdog Timer 11.3 Operation 11.3.1 Oscillation Stabilization Wait Operation Oscillation Stabilization Wait Operation The oscillation stabilization wait operation is for the oscillation circuit recovering from stop mode. The oscillation stabilization wait time is automatically inserted when the reset state is released. The oscillation stabilization wait is not operated with the self-reset by the reset control register (RSTCTR).
Page 344: Watchdog Operation
Chapter 11 Watchdog Timer 11.3.2 Watchdog Operation The watchdog timer counts the oscillation frequency as a clock source. If the watchdog timer is overflowed, the watchdog interrupt (WD0VFIRQ) is generated as a non-maskable interrupt (NMI). The watchdog timer control register (WDCTR) sets when the watchdog timer is released and how long the time-out period should be. Watchdog Timer Operation When the watchdog timer is used, constant clear in program is needed to prevent an overflow of the watchdog timer.
Page 345 Chapter 11 Watchdog Timer Detecting Incorrect Code Execution The watchdog timer detects error when it overflows. When the watchdog timer detects any error, the watchdog interrupt (WD0VFIRQ) is generated as a non maskable interrupt (NMI). Overflow Watchdog timer count value Count reset by writing a "1"...
Page 346: Self-Reset Operation
Chapter 11 Watchdog Timer 11.3.3 Self-reset Operation Self-reset operation is to reset the internal chip software. Self-reset Operation A self-reset is generated by setting the CHIPRST flag of the reset control register (RSTCTR) from “0” to “1”. A s elf-reset is not operated if the CHIPRST flag set to “1” when it contains “1”. The CHIPRST flag retains the value after the self-reset.
Page 347: Chapter 12 Serial Interface 0 And 1
XII.. Chapter 12 Serial interface 0 and 1...
Page 348: Overview
Chapter 12 Serial interface 0 and 1 12.1 Overview Serial interface 0 and 1 can be used for both communication types of clock synchronous and UART (Universal Asynchronous Receiver). 12.1.1 Functions Table: 12.1.1 shows functions for serial interface 0 and 1. Table:12.1.1 Functions for Serial Interface 0 and 1 Serial0 Serial1...
Page 349: Block Diagram
Chapter 12 Serial interface 0 and 1 12.1.2 Block Diagram Serial Interface 0 and 1 Block Diagram Figure:12.1.1 Serial Interface 0 and 1 Block Diagram Overview XII - 3...
Page 350: Control Registers
Chapter 12 Serial interface 0 and 1 12.2 Control Registers 12.2.1 Registers Table: 12.2.1 shows registers used to control serial interface 0 and 1. Table:12.2.1 Control Registers for Serial Interface 0 and 1 Register Address Access size Function Page SC0RB 0x0000A104 8,16 Serial 0 reception register...
Page 351: Serial Interface Reception And Transmission Registers
Chapter 12 Serial interface 0 and 1 12.2.2 Serial Interface Reception and Transmission Registers Serial interface 0 and 1 each 8-bit data buffer register for transmission/reception. Data is loaded by reading data from the SCnRB register during serial reception. Reception data can be loaded when an interrupt occurs or when the SCnRXA flag of the SCnSTR register is “1”. In the case of 7-bit transmission, the MSB (bit 7) is “0”.
Page 352: Serial Interface Control Registers
Chapter 12 Serial interface 0 and 1 12.2.3 Serial Interface Control Registers The serial control register is used to set the operation conditions for the corresponding serial interface. This regis- ter controls parameters including clock source selection, parity bit selection, protocol selection and enabling of transmission and reception.
Page 353 Chapter 12 Serial interface 0 and 1 Serial 1 Control Register (SC1CTR: 0x0000A110) [8,16-bit Access Register] Flag SCA1 SCA1 Rese Rese Rese 1TEN rved 1PTL rved rved At reset Access Flag Description Setting condition Transmission enable 0: Transmission disabled SCA1TEN 1: Transmission enabled Reception enable 0: Reception disabled...
Page 354: Serial Status Registers
Chapter 12 Serial interface 0 and 1 12.2.4 Serial Status Registers The serial status register indicates operation status for serial interface. Table: 12.2.2 shows generation cause and flag update timing for SCAnFE, SCAnPE, an SCAnOE flags. Table:12.2.2 Generation Cause and Update Timing of Flags Related with Error Error Generation cause Flag update timing...
Page 355 Chapter 12 Serial interface 0 and 1 Serial 1 Status Register (SC1STR: 0x0000A119) [8,16-bit Access Register] Flag SCA1 SCA1 SCA1 SCA1 SCA1 SCA1 TBSY RBSY At reset Access Flag Description Setting condition Transmission status flag 0: Can transmit SCA1TBSY 1: On transmitting Reception status flag 0: Can receive SCA1RBSY...
Page 356: Serial Clock Selection Registers
Chapter 12 Serial interface 0 and 1 12.2.5 Serial Clock Selection Registers Serial clock selection register is used to set a clock for serial interface. Serial Clock Selection Register (SIFCLK: 0x0000A10E) [8,16-bit Access Register] Flag CKS1 CKS0 CKS1 CKS0 CKS1 CKS0 At reset Access...
Page 357: Operation
Chapter 12 Serial interface 0 and 1 12.3 Operation 12.3.1 Operation Serial interface 0 and 1 can be used for both clock synchronous and duplex UART serial interfaces. 12.3.2 Clock Synchronous Serial Interface Activation Factor for Communication Table: 12.3.1 shows activation factors for communication. At master communication, the transfer clock is gener- ated by setting data to the serial transmission register SCnTB.
Page 358 Chapter 12 Serial interface 0 and 1 Setting Transfer Bit 7 to 8 bits can be set as transfer bit count. Set the bit count by the SCAnLN flag of the SCnCTR register. The SCAnLN flag holds the former set value until it is set again. Setting First Transfer Bit The SCAnOD flag of the SCnCTR register can set the first transfer bit.
Page 359 Chapter 12 Serial interface 0 and 1 Setting Clock The SCnCKS1 to 0 of the SIFCLK register selects a clock source from the internal clock (clock master), or the SBTn pins selects it from the external clock (clock slave) by . Table:12.3.3 Synchronous Serial Interface Clock Source Clock source Serial interfaces 0 and 1...
Page 360 Chapter 12 Serial interface 0 and 1 Transmission Timing At master Tmax=3.5T Clock (SBTn pin) Output pin (SBOn pin) Transfer bit counter SC2TBSY (Data set in SBnTB) Interrupt(SCnTIRQ) Figure:12.3.3 Transmission Timing (At Falling Edge) Reception Timing At master Tmax=3.5T Clock (SBTn pin) Input pin (SBIn pin)
Page 361 Chapter 12 Serial interface 0 and 1 Transmission/Reception Timing As data is received at the opposite edge timing ( rising edge) of the falling output edge of transmission data, out- put transmission data at the falling edge and input reception data at the rising edge for the equipment with which the microcontroller is exchanging data.
Page 362: Setup Example
Chapter 12 Serial interface 0 and 1 12.3.3 Setup Example Transmission/Reception Setup Example The setup example for clock synchronous serial communication with serial 0 is shown. Table: 12.3.4 shows the conditions at transmission/reception. Table:12.3.4 Setup Example for Synchronous Serial Interface Transmission/Reception Setup item Description SBI2/SBO2 pin setting...
Page 363 Chapter 12 Serial interface 0 and 1 Setup Procedure Description (6) Set the SC0CTR register (6) Set the SCA0PTL flag of the SC0CTR register to “1” to Set the protocol select synchronous communication. SC0CTR(0x0000A100) Set the SCA0OD flag of the SC0CTR register to “1” to bp11: SCA0PTL=1 set the first transfer bit to MSB.
Page 364: Uart Serial Interface
Chapter 12 Serial interface 0 and 1 12.3.4 UART Serial Interface Activation Factor for Communication At transmission, if any data is set to the transmission data buffer SCnTB, a start condition is generated to start transfer. At reception, if a start condition is received, communication is started. In reception, if the data length of “L”...
Page 365 Chapter 12 Serial interface 0 and 1 Clock Setup Transfer clock is not necessary for UART communication itself but necessary for setup of data transmission/ reception timing in the serial interface. Select the timer to be used as a baud rate timer by the SISFCLK register. Break Status Transmission Control Setup The SCAnBRE flag of the SCnCTR register generates the break status.
Page 366 Chapter 12 Serial interface 0 and 1 Setting Data I/O Pin 2 channels (data output pin (SBO pin), data input pin (SBIn pin)) are used for communication. Reception Data Flag Operation Data is automatically stored to SCnRB from the internal shift register when the reception complete interrupt SCn- RIRQ is generated.
Page 367 Chapter 12 Serial interface 0 and 1 Transmission Timing SBOn Parity Stop Stop SCAnTBSY (Data set in SBnTB) Interrupt (SCnTIRQ) Figure:12.3.7 Transmission Timing ( With Parity bit) SBOn Stop Stop SCAnTBSY (Data set in SBnTB) Interrupt (SCnTIRQ) Figure:12.3.8 Transmission Timing ( Without Parity bit) Operation XII - 21...
Page 368 Chapter 12 Serial interface 0 and 1 Reception Timing Tmin=0.5T SBIn pin Parity Stop Stop SCAnRBSY Input start condition Interrupt (SCnRIRQ) Figure:12.3.9 Reception Timing ( With Parity bit) Tmin=0.5T SBIn pin Stop Stop SCAnRBSY Input start condition Interrupt (SCnRIRQ) Figure:12.3.10 Reception Timing (Without Parity bit) XII - 22 Operation...
Page 369 Chapter 12 Serial interface 0 and 1 Transfer Speed Setup Any transfer rate can be set by using baud rate timer (timer 14, timer 15 and timer 16). Table: 12.3.8 shows the setup example of the transfer speed. Table:12.3.8 UART Serial Interface Transfer Speed Setting Register Setup Register Page...
Page 370: Uart Serial Interface Setup
Chapter 12 Serial interface 0 and 1 12.3.5 UART Serial Interface Setup UART Serial Interface Setup The setup example for UART transmission/reception with serial 0 is shown. Table: 12.3.10 shows the condition for transmission/reception. Table:12.3.10 UART Interface Transmission/Reception Condition Setup item Description SBI0/SBO0 pin setting Independent (2 channels)
Page 371 Chapter 12 Serial interface 0 and 1 Setup Procedure Description (5) Set the SC0CTR register (5) Set the SCA0PTL flag of the SC0CTR register to “0” to Set the protocol select the UART (start-stop) communication. SC0CTR(0x0000A100) Set the SCA0OD flag of the SC0CTR register to “1” to bp11: SCA0PTL=0 set the first transfer bit to MSB.
Page 372 Chapter 12 Serial interface 0 and 1 XII - 26 Operation...
Page 373: Chapter 13 Serial Interface 2
XIII.. Chapter 13 Serial Interface 2...
Page 374: Overview
Chapter 13 Serial Interface 2 13.1 Overview Serial interface 2 can be used for both communication types of clock synchronous and UART (Universal Asyn- chronous Receiver). 13.1.1 Functions Table: 13.1.1 shows functions with serial interface 2. Table:13.1.1 Serial Interface 2 Functions Communication type Clock synchronous UART (full duplex)
Page 375: Block Diagram
Chapter 13 Serial Interface 2 13.1.2 Block Diagram Serial Interface 2 Block Diagram Clock Selection Figure:13.1.1 Serial Interface 2 Block Diagram Overview XIII - 3...
Page 376: Control Registers
Chapter 13 Serial Interface 2 13.2 Control Registers 13.2.1 Registers Table: 13.2.1 shows registers that control serial interface 2. Table:13.2.1 Serial Interface 2 Control Registers Register Address Access size Function Page SC2RB 0x0000A12C 8,16 Serial interface 2 reception data buffer XIII-5 SC2TB 0x0000A130...
Page 377: Serial Interface 2 Data Buffer Register
Chapter 13 Serial Interface 2 13.2.2 Serial Interface 2 Data Buffer Register Serial interface 2 has each 8-bit data buffer register for transmission and reception. Serial Interface 2 Reception Data Buffer (SC2RB: 0x0000A12C) [8,16-Access Register] Flag × × × × ×...
Page 378: Serial Interface 2 Mode Register
Chapter 13 Serial Interface 2 13.2.3 Serial Interface 2 Mode Register These registers are readable/writable 8-bit registers that control serial interface 2 Serial Interface 2 Mode Register 0 (SC2CTR0: 0x0000A120) [8-bit Access Register] Table:13.2.2 Serial Interface 2 Mode Register 0 Flag LNG2 LNG1...
Page 379 Chapter 13 Serial Interface 2 Serial Interface 2 Mode Register 1 (SC2CTR1: 0x0000A121) [8-bit Access Register] Flag SBTS SBIS SBOS At reset Access Flag Description Setting condition Serial data input pin selection 0: Data input from SB12 SC2IOM 1: Data input from SB02 SBT2 pin function selection 0: Port SC2SBTS...
Page 380 Chapter 13 Serial Interface 2 Serial Interface 2 Mode Register 2 (SC2CTR2: 0x0000A124) [8-bit Access Register] Flag BRKF BRKE At reset Access Flag Description Setting Condition Frame mode specification 00: 7 data bits + 1 stop bit SC2FM1 01: 7 data bits + 2 stop bits SC2FM0 10: 8 data bits + 1 stop bit 11: 8 data bits + 2 stop bits...
Page 381 Chapter 13 Serial Interface 2 Serial Interface 2 Mode Register 3 (SC2CTR3: 0x0000A125) [8-bit Access Register] Flag FDC1 FDC0 PSCE PSC2 PSC1 PSC0 At reset Access Flag Description Setting condition Output selection after SB0 last 00: Fixed at "1"(High) output SC2FDC 1 data transmission 10: Fixed at "0"(Low) output...
Page 382 Chapter 13 Serial Interface 2 Serial Interface 2 Status Register (SC2STR: 0x0000A128) [8,16-bit Access Register] Flag TBSY RBSY TEMP REMP At reset Access Flag Description Setting condition Serial bus busy status 0: Other than serial transmission SC2TBSY 1: Serial transmission Serial bus busy status 0: Other than serial reception SC2RBSY...
Page 383: Operation
Chapter 13 Serial Interface 2 13.3 Operation 13.3.1 Serial Interface 2 Operation Serial interface 2 is used as clock synchronous and full duplex UART serial interface. 13.3.2 Clock Synchronous Serial Interface Activation Factors for Communication Table: 13.3.1 shows activation factors for communication. In the case of master communication, a transfer clock is generated by setting data to the transfer data buffer SC2TB or by receiving a start condition.
Page 384 Chapter 13 Serial Interface 2 Reception Data Buffer The reception data buffer SC2RB is a spare buffer that pushes the received data by the reception shift register. After the communication complete interrupt SC2TIRQ is generated, data stored in the reception shift register is automatically stored in the reception data buffer SC2RB.
Page 385 Chapter 13 Serial Interface 2 Transmission Bit Count and First Transfer Bit In transmission, when the transfer bit count is from 1 to 7 bits, the method for data storage to the transmission data buffer differs depending on the first transfer bit. When MSB is the first bit, store data to use the upper bits of SC2TB.
Page 386 Chapter 13 Serial Interface 2 Setting Edge for Output/Input The SC2CE1 flag of the SC2CTR0 register sets the edge of transmission data output and the edge of reception data input. Transmission data is output in synchronization with the falling edge of the clock when the SC2CE1 flag = “0”...
Page 387 Chapter 13 Serial Interface 2 Last Bit of Transmission Data Table: 13.3.4 shows the last bit data output holding period at transmission and minimum data input period of the last bit at reception. At slave, an internal clock should be set to secure data holding time at data transmission. Table:13.3.4 Last Bit Data Length of Data Transfer Last bit data holding period at transmission Last bit data input period at reception...
Page 388 Chapter 13 Serial Interface 2 Setting Data I/O Pin Communication modes have 2 types: 3 channels (clock pin (SBT2 pin), data output pin (SBO2 pin) and data input pin (SBI2 pin )) and 2 channels (clock pin SBT2 pin) and data I/O pin (SBO2 pin)). The SBO2 pin can be used only for serial data input.
Page 389 Chapter 13 Serial Interface 2 Transmission BUSY Flag Operation The SC2TBSY flag of the SC2STR register is set if the SC2SBOS flag of the SC2CTR1 register is set to “1” when data is set in SC2TB or a when a start condition is recognized while “serial data output” is selected with the SC2SBOS flag of the SC2CTR1 register.
Page 390 Chapter 13 Serial Interface 2 Transmission Timing At master At slave Tmax=2.5T Tmax=2T Clock (SBT2 Output pin (SBO2 Transfer bit counter SC2TBSY (Data set to SC2TB) Interrupt (SC2TIRQ) Figure:13.3.5 Transmission Timing (Falling Edge, With Start Condition) At master At slave Tmax=2T Tmax=3.5T Clock...
Page 391 Chapter 13 Serial Interface 2 At master At slave Tmax=2.5T Tmax=2T Clock (SBT2 Output pin (SBO2 Transfer bit counter SC2TBSY (Data set to SC2TB) Interrupt (SC2TIRQ) Figure:13.3.7 Transmission Timing (Rising Edge, With Start Condition) At slave At master Tmax=2T Tmax=3.5T Clock (SBT2 Output pin...
Page 392 Chapter 13 Serial Interface 2 Reception Timing Clock (SBT2 Input pin (SBO2 Transfer bit counter SC2RBSY Interrupt (SC2TIRQ) Figure:13.3.9 Reception Timing (Rising Edge, With Start Condition) At master Tmax=3.5T Clock (SBT2 Input pin (SBO2 pin Transfer bit counter SC2RBSY (Data set to SC2TB) Interrupt (SC2TIRQ) Figure:13.3.10 Reception Timing (Rising Edge, Without Start Condition)
Page 393 Chapter 13 Serial Interface 2 Clock (SBT2 Input pin (SBO2 Transfer bit counter SC2RBSY Interrupt (SC2TIRQ) Figure:13.3.11 Reception Timing (Falling Edge, With Start Condition) At master Tmax=3.5T Clock (SBT2 Input pin (SBO2 Transfer bit counter SC2RBSY (Data set to SC2TB) Interrupt (SC2TIRQ) Figure:13.3.12 Reception Timing (Falling Edge, Without Start Condition)
Page 394 Chapter 13 Serial Interface 2 Transmission and Reception As data is received at the opposite edge of transmission data, set the polarity of the reception data input edge to the opposite of the transmission data output edge. Then, set to “without start condition” when performing trans- mission and reception at the same time.
Page 395: Setup Example
Chapter 13 Serial Interface 2 13.3.3 Setup Example Transmission/Reception Setup Example Here is the setup example for transmission/reception of clock synchronous communication with serial interface 2. Table: 13.3.7 shows the conditions for transmission/reception. Table:13.3.7 Conditions of Synchronous Serial Interface Transmission/Reception Setting item Description SBI2/SBO2 pin setting...
Page 396 Chapter 13 Serial Interface 2 Setup Procedure Description (6) Set the pin function (6) Set the P17M flag of the P1MD register to “1” to set the P1MD(0x0000A031) SBO2 pin function, the P20M flag of the P2MD register bp7: P17M=1 to “1”...
Page 397: Uart Serial Interface
Chapter 13 Serial Interface 2 13.3.4 UART Serial Interface Serial interface 2 is capable of duplex UART communication. Table: 13.3.8 shows UART serial interface func- tions. Table:13.3.8 UART Serial Interface Functions Communication style UART (duplex) Interrupt SC2TIRQ (transmission), SC2RIRQ (reception) SBO2 (I/O) SBI2 (input) First transfer bit specification...
Page 398 Chapter 13 Serial Interface 2 Setting Transfer Bit Count Transfer bit count is set automatically when a frame mode is specified with the SC2FM1-0 flags of the SC2CTR2 register. When the SC2CMD flag of the SC2CTR1 register is set to “1” and UART communication is selected , the setting in the synchronous serial transfer bit count selection flag SC2LNG2-0 f the SC2CTR0 register becomes invalid.
Page 399 Chapter 13 Serial Interface 2 Setting Frame Mode and Parity Check Figure: 13.3.17 shows the data format at UART communication. Frame Start Parity Stop Character bit Figure:13.3.17 UART Serial Interface Transmission/Reception Data Format Transmission/reception data contain start bit, character bit, parity bit, and stop bit. Table: 13.3.9 shows the types to be set.
Page 400 Chapter 13 Serial Interface 2 Setting Data I/O PIn Communication modes can be selected from 2 channels (data output pin (SBO2 pin) and data input pin (SBI2 pin)), or 1 channel (data I/O pin (SBO2 pin)). The SBI2 pin can be used only for serial data input. The SBI2 pin can be used for both serial data input and output.
Page 401 Chapter 13 Serial Interface 2 Reception Error Reception errors can be classified under 3 types, overrun error, parity error and framing error. Reception error can be determined by checking the SC2ORE, SC2PEK and SC2FEF flags of the SC2STR register. If an error is found from any of these flags, the SC2ERE flag of the SC2STR register is set to “1”.
Page 402 Chapter 13 Serial Interface 2 SBO2 pin Stop Stop Tmax=2.5T SC2TBSY (Data set in SC2TB) Interrupt (SC2TIRQ) Figure:13.3.19 Transmission Timing (Without Parity bit) Reception Timing Tmin=0.5T SBI2 pin Parity Stop Stop SC2RBSY Input start condition Interrupt (SC2RIRQ) Figure:13.3.20 Reception Timing (With Parity bit) Tmin=0.5T SBI2 pin Stop...
Page 403 Chapter 13 Serial Interface 2 Setting Transfer Speed Baud rate timers (timer 14, timer 15 and timer 16) can set any transfer rate. Table: 13.3.13 shows an example of setting transfer speed. Table:13.3.13 Register for Setting UART Serial Interface Transfer Speed Description Register Page...
Page 404 Chapter 13 Serial Interface 2 Table:13.3.14 Set value of Transfer Speed (Base Register value: hexadecimal) XIII - 32 Operation...
Page 405: Setup Example
Chapter 13 Serial Interface 2 13.3.5 Setup Example UART Serial Interface Setup Example The setup example of UART transmission/reception with serial interface 2 is shown. Table: 13.3.14 shows the conditions for transmission/reception. Table:13.3.15 Condition of UART Interface Transmission/Reception Setting item Description SBI2/SBO2 pin setting Independent (2 channels)
Page 406 Chapter 13 Serial Interface 2 Setup Procedure Description (7) Set the SC2CTR2 register (7) Set the SC2BRKE flag of the SC2CTR2 register to “0” to Control the output data select the serial data transmission. SC2CTR2(0x0000A124) Set the SC2PM1-0 flags of the SC2CTR2 register to bp0: SC2BRKE=0 “00”...
Page 407: Chapter 14 A/D Converter
XIV.. Chapter 14 A/D Converter...
Page 408: Overview
Chapter 14 A/D Converter 14.1 Overview This LSI has an A/D converter with 10 bit resolutions and up to 16-channel analog signals can be processed with 3 converters. It contains a built-in sample hold circuit. 6 types of conversion reference clocks can be switched by software.
Page 409: Configuration
Chapter 14 A/D Converter 14.1.2 Configuration A/D Converter Configuration Figure:14.1.1 A/D Converter Configuration Overview XIV - 3...
Page 410: Control Registers
Chapter 14 A/D Converter 14.2 Control Registers A/D converter consists of the conversion control register, conversion data buffer and start selection register. 14.2.1 Registers Table: 14.2.1 shows the registers used to control A/D converter. Table:14.2.1 A/D Converter Control Registers Register Address Access size Function...
Page 411 Chapter 14 A/D Converter Register Address Access size Function Page AN2CTR0 0x0000A480 8,16 A/D2 conversion control register 0 XIV-8 AN2CTR1 0x0000A484 8,16 A/D2 conversion control register1 XIV-11 ADST2 0x0000A488 A/D2 start trigger selection register XIV-13 AN2CTREGA 0x0000A48C A/D2 start trigger count register XIV-16 AN2BUF06 0x0000A490...
Page 412: Control Registers
Chapter 14 A/D Converter 14.2.2 Control Registers These registers are 16-bit readable/writable registers which control an A/D converter. A/D0 Conversion Control Register 0 (AN0CTR0: 0x0000A400) [8,16-bit Access Register] Flag TRG0 At reset Access Flag Description Setting condition 15-13 Edge detection at external trigger con- Reserved EXTRG0 version...
Page 413 Chapter 14 A/D Converter A/D1 Conversion Control Register 0 (AN1CTR0: 0x0000A440) [8,16-bit Access Register] Flag TRG1 At reset Access Flag Description Setting condition 15-13 Edge detection at external trigger con- Reserved EXTRG1 version 000: ADIN02 Channel number at any single channel 001: ADIN03 conversion 010: ADIN04...
Page 414 Chapter 14 A/D Converter A/D2 Converter Control Register 0 (AN2CTR0: 0x0000A480) [8,16-bit Access Register] Flag At reset Access Flag Description Setting condition 15-13 Edge detection at external trigger con- Reserved TRG2 version 0000: ADIN06 0001: ADIN07 0010: ADIN08 0011: ADIN09 0100: ADIN10 Channel number at any single channel 0101: ADIN11...
Page 415 Chapter 14 A/D Converter A/D0 Conversion Control Register 1 (AN0CTR1: 0x0000A404) [8,16-bit Control Register] Flag Rese Rese Rese Rese rved rved rved rved At reset Access Flag Description Setting condition 14-11 Reserved Write “0” 000: ADIN00 001: ADIN01 010: ADIN02 AN0CH0B2 Channel number at generation of trigger B.
Page 416 Chapter 14 A/D Converter A/D1 Conversion Control Register 1 (AN1CTR1: 0x0000A444) [8,16-bit Control Register] Flag Rese Rese Rese Rese rved rved rved rved At reset Access Flag Description Setting condition 14-11 Reserved Write “0” 000: ADIN02 001: ADIN03 010: ADIN04 AN1CH0B2 Channel number at generation of trigger B.
Page 417 Chapter 14 A/D Converter A/D2 Conversion Control Register 1 (AN2CTR1: 0x0000A484) [8,16-bit Control Register] Flag At reset Access Flag Description Setting condition 15-6 00: 1 cycle AN2SHC1 01: 2 cycles Sampling/hold cycle mode AN2SHC0 10: 4 cycles 11: 6 cycles 0000: ADIN06 0001: ADIN07 0010: ADIN08...
Page 418: A/D Start Trigger Selection Registers
Chapter 14 A/D Converter 14.2.3 A/D Start Trigger Selection Registers A/D start trigger selection registers are used for selecting each A/D conversion start trigger. A/D0 Start Trigger Selection Register (ADST0: 0x0000A408) [8-bit Access Register] Flag AD0B AD0B AD0B AD0A AD0A AD0A At reset Access...
Page 419 Chapter 14 A/D Converter A/D1 Start Trigger Selection Register (ADST1: 0x0000A448) [8-bit Access Register] Flag AD1B AD1B AD1B AD1A AD1A AD1A At reset Access Flag Description Setting condition 000: PWM0 overflow 001: PWM0 underflow 010: Timer 12 compare A AD1BST2 011: Timer 12 compare B AD1BST1 AD1 start trigger selection B...
Page 420: A/D Start Trigger Count Registers
Chapter 14 A/D Converter 14.2.4 A/D Start Trigger Count Registers A/D start trigger count registers are used for counting each A/D conversion start trigger. AD starts after the set number is counted. A/D0 Start Trigger A Count Register (AN0CTREGA: 0x0000A40C) [8-bit Access Register] Flag AN0A AN0A...
Page 421 Chapter 14 A/D Converter A/D1Start Trigger A Count Register (AN1CTREGA: 0x0000A44C) [8-bit Access Register] Flag AN1A AN1A AN1A AN1A AN1A AN1A AN1A AN1A CNT3I CNT2I CNT1I CNT0I CNT3 CNT2 CNT1 CNT0 At reset Access Flag Description Setting condition AN1ACNT3I Setting the number of AD1 external trig- 0000~1111: 0 to 15 times AN1ACNT2I ger A counting...
Page 422 Chapter 14 A/D Converter A/D2 Start Trigger Count Register (AN2CTREGA: 0x0000A48C) [8-bit Access Register] Flag AN2A AN2A AN2A AN2A AN2A AN2A AN2A AN2A CNT3I CNT2I CNT1I CNT0I CNT3 CNT2 CNT1 CNT0 At reset Access Flag Description Setting condition AN2ACNT3I Setting the number of AD2 external trig- 0000~1111: 0 to 15 times AN2ACNT2I ger counting...
Page 423: Data Buffers
Chapter 14 A/D Converter 14.2.5 Data Buffers A/D conversion result (10 bits) is stored in A/D conversion data buffers. A/D0 Conversion Data Buffer 0 (AN0BUF00: 0x0000A410) [16-bit Access Register] Flag × × × × × × × × × × At reset Access Flag...
Page 424 Chapter 14 A/D Converter A/D0 Conversion Data Buffer 3 (AN0BUF03: 0x0000A41C) [16-bit Access Register] Flag × × × × × × × × × × At reset Access Flag Description Setting condition 15-10 AN0BUF39 A/D0 conversion result of ADIN03 pin A/D0 conversion result of ADIN03 pin AN0BUF30 A/D0 Conversion Data Buffer 4 (AN0BUF04: 0x0000A420) [16-bit Access Register]...
Page 425 Chapter 14 A/D Converter A/D0 Conversion Data Buffer 0B (AN0BUF0B: 0x0000A430) [16-bit Access Register] Flag × × × × × × × × × × At reset Access Flag Description Setting condition 15-10 Conversion result of AD input pin Conversion result of AD input pin selected with conversion channel AN0BUF0B9 selected with conversion channel selec- selection (AN0CH0B2-0) at trigger B generation of AD0 conver-...
Page 426 Chapter 14 A/D Converter A/D1 Conversion Data Buffer 2 (AN1BUF02: 0x0000A450) [16-bit Access Register] Flag × × × × × × × × × × At reset Access Flag Description Setting condition 15-10 AN1BUF29 A/D1 conversion result of ADIN02 pin A/D1 conversion result of ADIN02 pin AN1BUF20 A/D1 Conversion Data Buffer 3(AN1BUF03: 0x0000A454) [16-bit Access Register]...
Page 427 Chapter 14 A/D Converter A/D1 Conversion Data Buffer 5 (AN1BUF05: 0x0000A45C) [16-bit Access Register] Flag × × × × × × × × × × At reset Access Flag Description Setting condition 15-10 AN1BUF59 A/D1 conversion result of ADIN05 pin A/D1 conversion result of ADIN05 pin AN1BUF50 A/D1 Conversion Data Buffer 6 (AN1BUF06: 0x0000A460) [16-bit Access Register]...
Page 428 Chapter 14 A/D Converter A/D1 Conversion Data Buffer 8 (AN1BUF08: 0x0000A468) [16-bit Access Register] Flag × × × × × × × × × × At reset Access Flag Description Setting condition 15-10 AN1BUF89 A/D1 conversion result of ADIN08 pin A/D1 conversion result of ADIN08 pin AN1BUF80 A/D1 Conversion Data Buffer 9 (AN1BUF09: 0x0000A46C) [16-bit Access Register]...
Page 429 Chapter 14 A/D Converter A/D2 Conversion Data Buffer 6 (AN2BUF06: 0x0000A490) [16-bit Access Register] Flag × × × × × × × × × × At reset Access Flag Description Setting condition 15-10 AN2BUF69 A/D2 conversion result of ADIN06 pin A/D2 conversion result of ADIN06 pin AN2BUF60 A/D2 Conversion Data Buffer 7 (AN2BUF07: 0x0000A494) [16-bit Access Register]...
Page 430 Chapter 14 A/D Converter A/D2 Conversion Data Buffer 9 (AN2BUF09: 0x0000A49C) [16-bit Access Register] Flag × × × × × × × × × × At reset Access Flag Description Setting condition 15-10 AN2BUF99 A/D2 conversion result of ADIN09 pin A/D2 conversion result of ADIN09 pin AN2BUF90 A/D2 Conversion Data Buffer 10 (AN2BUF10: 0x0000A4A0) [16-bit Access Register]...
Page 431 Chapter 14 A/D Converter A/D2 Conversion Data Buffer 12 (AN2BUF12: 0x0000A4A8) [16-bit Access Register] Flag × × × × × × × × × × At reset Access Flag Description Setting condition 15-10 AN2BUF129 A/D2 conversion result of ADIN12 pin A/D2 conversion result of ADIN12 pin AN2BUF120 A/D2 Conversion Data Buffer 13 (AN2BUF13: 0x0000A4AC) [16-bit Access Register]...
Page 432 Chapter 14 A/D Converter A/D2 Conversion Data Buffer 15 (AN2BUF15: 0x0000A4B4) [16-bit Access Register] Flag × × × × × × × × × × At reset Access Flag Description Setting condition 15-10 AN2BUF159 A/D2 conversion result of ADIN15 pin A/D2 conversion result of ADIN15 pin AN2BUF150 XIV - 26...
Page 433: Operation
Chapter 14 A/D Converter 14.3 Operation 14.3.1 A/D Converter Operation A/D Converter Timing Figure: 14.3.1 shows A/D converter timing. The conversion time of A/D converter is the total of the sampling hold (S/H) time , 10 bit conversion time and transfer time. When S/H time is 1 cycle, conversion time is 12 con- version clock cycles.
Page 434 Chapter 14 A/D Converter Setting Sampling/Hold Time Sampling/hold time can be selected from 1, 2 , 4 and 6 cycles of the conversion clock. Select the proper value with the A/D input impedance. If the A/D input impedance is high, select 6 cycles. Selecting Operation Mode Operation mode is set by the AN0MD1-0 flags of the AN0CTR0 register and the AN1MD1-0 flags of the AN1CTR0 register and the AN2MD1-0 flags of the AN2CTR0 register.
Page 435 Chapter 14 A/D Converter Power-down Mode Power-down mode is used to minimize the standby power requirement. Set the ANnOFF flag of the ANnCTR0 register to “0”, for power-down mode and to “1” for operation mode. Set it to operation mode at conversion oper- ation.
Page 436 Chapter 14 A/D Converter Multiple Channels/One-time Conversion for Each (AD0 , AD1) Continuous multiple A/D input is converted only once. The A/D interrupt is generated at the same time when all conversions of multiple channels end. Set the first channel to be converted by the ANnCH2-0 flags of the ANnCTR0 register and the last channel by the ANnNCH2-0 flags of the ANnCTR1 register.
Page 437 Chapter 14 A/D Converter Any Single Channel/Continuous Conversion (AD0, AD1) A/D input of single channel is converted continuously. The A/D interrupt is generated every time conversion ends. Set the channel number to be converted to the ANnCH2-0 flags of the ANnCTR0 register (conversion chan- nel at any single channel conversion).
Page 438 Chapter 14 A/D Converter Multiple Channels/Continuous Conversion (AD0, AD1) Continuous multiple A/D input is converted continuously. The A/D interrupt is generated every time all conver- sions of multiple channels end. Set the first channel to be converted by the ANnCH2-0 flags of the ANnCTR0 and the last channel by the ANnNCH2-0 flags of the ANnCTR1 register.
Page 439: Setup Example
Chapter 14 A/D Converter 14.3.2 Setup Example Setup Example for Single Channel/One-time Conversion The following shows an example of 1-channel A/D converter. Analog voltage (VDD to VSS) is fed to the ANIN00 pin to obtain A/D conversion result. ADIN00 1000 pF Figure:14.3.6 1-Channel A/D Conversion Table:14.3.5 Conditions of 1-Channel A/D Conversion Setting item...
Page 440 Chapter 14 A/D Converter An example setup procedure, with a description of each step is shown below. Setup Procedure Description (1) Stop the A/D converter operation (1) Set the AN0EN and AN0TRG flags of the A/D0 AN0CTR0(0x0000A400) conversion control register (AN0CTR0) to “0” to stop bp7: AN0EN=0 the A/D conversion.
Page 441 A/D converter result can be obtained with feeding analog voltage by the ADIN00 and ADIN01 pins. Conversion is performed regularly with the timer 12 compare A matching. Volume1 Volume2 Volume3 AD conversion MN103S CPU Core Data buffer External trigger( Timer 12 compareA match ) Figure:14.3.7 1-channel A/D Conversion Table:14.3.6 Conditions for Multiple Channel A/D Conversion ·...
Page 442 Chapter 14 A/D Converter Setup Procedure Description (4) Set the AD0: Set the AN0CTR0 register (4) Set the AN0MD1-0 flags of the AN0CTR0 register to “01” Set the operation mode to set “multiple channels/one-timer conversion” to AN0CTR0(0x0000A400) operation mode. bp1-0: AN0MD1-0=01 Set the AN0CK2-0 flags of the AN0CTR0 register to Set the conversion clock “011”...
Page 443 Chapter 14 A/D Converter Setup Procedure Description (13) Set the timer 12: Select the timer compare/ (13) Set the compare register (double buffer) to the function capture A operation mode of the timer 12 compare/capture register by the TM12MDA(0x0000A284) TMAM1-0 flags of the timer 12 compare/capture A bp7-6: TMAM1-0=00 mode register (TM12MDA).
Page 444 Chapter 14 A/D Converter Setup Example of Multiple Channel A/D Converter Simultaneous Conversion Using PWM as External trigger A/D converter result can be obtained with feeding analog voltage by the ADIN00 and ADIN02 to activate A/D0 and A/D1 byPWM0 and by the ADIN01 and ADIN03 pins to activate A/D0 and A/D1 by PWM1. Conversion is performed regularly PWM0 underflow.
Page 445 Chapter 14 A/D Converter An example setup procedure, with a description of each step is shown below. Setup Procedure Description (1) Set the AD0: Stop the A/D converter (1) Set the AN0EN flag and the AN0TRG flag of the A/D0 operation conversion control register 0 (AN0CTR0) to “0”...
Page 446 Chapter 14 A/D Converter Setup Procedure Description (4) Set the AD0: Set the AN0CTR0 register (4) Set the AN0MD1-0 flags of the AN0CTR0 register to “00” Set the operation mode to set “any channels/one-time conversion for each” to AN0CTR0(0x0000A400) operation mode. bp1-0: AN0MD1-0=01 Set the AN0CK2-0 flags of the AN0CTR0 register to Set the conversion clock...
Page 447 Chapter 14 A/D Converter Setup Procedure Description (7) Set the AD1: Set the AN1CTR0 register (7) Set the AN1MD1-0 flags of the AN1CTR0 register to “00” Set the operation mode to set “any channels/one-time conversion for each” to AN1CTR0(0x0000A440) operation mode. bp1-0: AN1MD1-0=00 Set the AN1CK2-0 flags of the AN1CTR0 register to Set the conversion clock...
Page 448 Chapter 14 A/D Converter Setup Procedure Description (10) Set the AD2: Set the AN2CTR0 register (10) Set the AN2MD1-0 flags of the AN2CTR0 register to Set the operation mode “00” to set “any channels/one-time conversion for each” AN2CTR0(0x0000A480) to operation mode. bp1-0: AN2MD1-0=00 Set the AN2CK2-0 flags of the AN2CTR0 register to Set the conversion clock...
Page 449 Chapter 14 A/D Converter Setup Procedure Description (16) Read the A/D value (16) Read the A/D0 conversion data buffer 0B and A/D1 AN0BUF0B (0x0000A430) conversion data buffer 0B (AN0BUF0B, AN1BUF0B) AN1BUF0B (0x0000A470) by the AD0 complete B interrupt processing after the A/ D0 conversion is completed.
Page 450: Cautions
Chapter 14 A/D Converter 14.3.3 Cautions A/D converter can be damaged by noise easily; therefore, anti-noise measures should be taken adequately. The following shows cautions for anti-noise measures and the recommended circuit when A/D converter is used. Anti-noise Measures To A/D input (analog input pin ADINn), add condenser near the VSS pins of micro controller. ADIN00 ADIN15 Chip...
Page 451: Chapter 15 Regulator
XV.. Chapter 15 Regulator...
Page 452: Overview
Chapter 15 Regulator 15.1 Overview The regulator converts 5 V VDD which is supplied externally and supplies it into the internal circuit of the microcontroller. 15.1.1 Setup Insert a capacitor which is more than 10 µF between each VDD pin and VSS. And insert a capacitor which is more then 1 µF between each VDD2 and VSS.
Page 453: Chapter 16 Appendix
XVI.. Chapter 16 Appendix...
Page 454: Cautions For Circuit Setup
Chapter 16 Appendix 16.1 Cautions for Circuit Setup 16.1.1 General Usage Connection of V pin and V All of the VDD and VSS pins should be connected directly to the power supply and GND in the external. Put them on printed circuit board after the location of LSI (package) pin is confirmed. Connection error may lead a fusion and breakdown of a microcontroller.
Page 455 Chapter 16 Appendix Unused Pin (Only for Input) Insert some 10 kΩ resistor to unused pins (only for input) to pull up or down. If the input is unstable, Pch transistor and Nch transistor of input inverter are on, and through current goes to the input circuit.
Page 456 Chapter 16 Appendix Unused Pins (for I/O) Unused I/O pins should be set according to pins’ condition at reset. If the output is high impedance (Pch / Nch transistor: output off) at reset, to stabilize input, set some 10 kΩ resistor to pull up or down. If the output is on at reset, set them open.
Page 457: Power Supply
Chapter 16 Appendix 16.1.3 Power Supply The Relation between Power Supply and Input Pin Voltage Input pin voltage should be supplied only after power supply is on. If this order is reversed, the destruction of microcontroller by a large current flow could be occurred. Input Input protection resister Generation of foward current...
Page 458: Power Supply Circuit
Chapter 16 Appendix 16.1.4 Power Supply Circuit Cautions for Setting Circuit with V The MOS logic such a microcontroller is high speed and high density; so, the power circuit should be designed, taking into consideration of AC line noise, ripple caused by LED driver. Figure: 16.1.7 shows an example for a circuit with VDD (Emitter follower type).
Page 459: Instruction Set
Chapter 16 Appendix 16.2 Instruction Set Instruction Set XVI - 7...
Page 460 Chapter 16 Appendix XVI - 8 Instruction Set...
Page 461 Chapter 16 Appendix Instruction Set XVI - 9...
Page 462 Chapter 16 Appendix XVI - 10 Instruction Set...
Page 463 Chapter 16 Appendix Instruction Set XVI - 11...
Page 464 Chapter 16 Appendix XVI - 12 Instruction Set...
Page 465 Chapter 16 Appendix Instruction Set XVI - 13...
Page 466 Chapter 16 Appendix XVI - 14 Instruction Set...
Page 467 Chapter 16 Appendix Instruction Set XVI - 15...
Page 468 Chapter 16 Appendix XVI - 16 Instruction Set...
Page 469 Chapter 16 Appendix Instruction Set XVI - 17...
Page 470 Chapter 16 Appendix XVI - 18 Instruction Set...
Page 471 Chapter 16 Appendix Instruction Set XVI - 19...
Page 472 Chapter 16 Appendix XVI - 20 Instruction Set...
Page 473 Chapter 16 Appendix Instruction Set XVI - 21...
Page 474 Chapter 16 Appendix XVI - 22 Instruction Set...
Page 475 Chapter 16 Appendix Instruction Set XVI - 23...
Page 476 Chapter 16 Appendix XVI - 24 Instruction Set...
Page 477 Chapter 16 Appendix Instruction Set XVI - 25...
Page 478 Chapter 16 Appendix XVI - 26 Instruction Set...
Page 479 Chapter 16 Appendix Instruction Set XVI - 27...
Page 480 Chapter 16 Appendix XVI - 28 Instruction Set...
Page 481 Chapter 16 Appendix Instruction Set XVI - 29...
Page 482: Instruction Map
Chapter 16 Appendix 16.3 Instruction Map 1st byte Upper/Lower MOVBU MOVHU MOVBU MOVHU MOVBU MOVHU MOVBU MOVHU D0,(abs16) D0,(abs16) D0,(abs16) D1,(abs16) D1,(abs16) D1,(abs16) D2,(abs16) D2,(abs16) D2,(abs16) D3,(abs16) D3,(abs16) D3,(abs16) EXTB Dn EXTBU Dn EXTH Dn EXTHU Dn ADD imm8,An MOV imm16,An ADD imm8,Dn MOV imm16,Dn MOV (abs16),Dn...
Page 483 Chapter 16 Appendix 2nd byte (1st byte: F1)) Instruction for 2-byte Upper/lower SUB Dm,Dn SUB Am,Dn SUB Dm,An SUB Am,An ADDC Dm,Dn ADD Am,Dn ADD Dm,An ADD Am,An SUBC Dm,Dn CMP Am,Dn CMP Dm,An MOV Am,Dn MOV Dm,An 2nd byte(1st byte:F2) Instruction for 2-byte Upper/lower AND Dm,Dn OR Dm,Dn...
Page 484 Chapter 16 Appendix 2nd byte (1st byte: F3) Instructions for 2-byte Upper/lower MOV (Di,Am),Dn MOV Dm,(Di,An) MOV (Di,Am),An MOV Am,(Di,An) 2nd byte(1st byte: F4) Instruction for 2-byte) Upper/lower MOVBU (Di,Am),Dn MOVBU Dm,(Di,An) MOVHU (Di,Am),Dn MOVHU Dm,(Di,An) XVI - 32 Instruction Map...
Page 485 Chapter 16 Appendix 2nd byte(1st byte:F5) Instruction for 2-byte Upper/lower UDF20 Dm,Dn UDF21 Dm,Dn UDF22 Dm,Dn UDF23 Dm,Dn UDF24 Dm,Dn UDF25 Dm,Dn UDF26 Dm,Dn UDF27 Dm,Dn UDF28 Dm,Dn UDF29 Dm,Dn UDF30 Dm,Dn UDF31 Dm,Dn UDF32 Dm,Dn UDF33 Dm,Dn UDF34 Dm,Dn UDF35 Dm,Dn 2nd byte (1st byte: F6) Instruction for 2-byte) Upper/lower...
Page 486 Chapter 16 Appendix 2nd byte (1st byte:F8) Instruction for 3-byte Upper/lower MOV (d8,Am),Dn MOV Dm,(d8,An) MOV (d8,Am),An MOV Am,(d8,An) MOVBU (d8,Am),Dn MOVBU Dm,(d8,An) MOVHU (d8,Am),Dn MOVHU Dm,(d8,An) MOVBU MOVHU MOVBU MOVHU MOVBU MOVHU MOVBU MOVHU D0,(d8,SP) D0,(d8,SP) D1,(d8,SP) D1,(d8,SP) D2,(d8,SP) D2,(d8,SP) D3,(d8,SP) D3,(d8,SP)
Page 487 Chapter 16 Appendix 2nd byte (1st byte: F4) Instruction for 4-byte Upper/lower MOV (d16,Am),Dn MOV Dm,(d16,An) MOV (d16,Am),An MOV Am,(d16,An) MOVBU (d16,Am),Dn MOVBU Dm,(d16,An) MOVHU (d16,Am),Dn MOVHU Dm,(d16,An) A0,(abs16) A1,(abs16) A2,(abs16) A3,(abs16) MOVBU MOVHU MOVBU MOVHU MOVBU MOVHU MOVBU MOVHU A0,(d16,SP) D0,(d16,SP) D0,(d16,SP)
Page 488 Chapter 16 Appendix 2nd byte (1st byte: FC) Instruction for 6-byte Upper/lower MOV (d32,Am),Dn MOV Dm,(d32,An) MOV (d32,Am),An MOV Am,(d32,An) MOVBU (d32,Am),Dn MOVBU Dm,(d32,An) MOVHU (d32,Am),Dn MOVHU Dm,(d32,An) MOVBU MOVHU MOVBU MOVHU MOVBU MOVHU MOVBU MOVHU A0,(abs32) D0,(abs32) D0,(abs32) D0,(abs32) A1,(abs32) D1,(abs32) D1,(abs32)
Page 489 Chapter 16 Appendix 2nd byte (1st byte: FE) Instruction for 7/5-byte Upper/lower BSET imm8, BCLR imm8, BTST imm8, (abs32) (abs32) (abs32) BSET imm8, BCLR imm8, BTST imm8, (abs16)* (abs16)* (abs16)* * : Installed for AM32. Not used for AM30/AM31. 2nd byte (1st byte:F7) reserved map Upper/lower Instruction Map XVI - 37...
Page 490: Extension Instruction Specification
Chapter 16 Appendix 16.4 Extension Instruction Specification 16.4.1 Arithmetic extension function Arithmetic Extension Function The block diagram is shown below in which extension arithmetic units are connected to this series CPU core. With the MN103S00 Series, multipliers capable of 32 × 32 multiply operation, multiply and accumulate arithmetic units capable of 32 ×...
Page 491 Chapter 16 Appendix Extension Instructions Description of symbols Symbols used for description of extension instructions are listed below. OP : Instruction operation Am, An : Address register (m, n=3 to 0) Dm, Dn : Data register (m, n=3 to 0 ) SP : Stack pointer imm :...
Page 492 Chapter 16 Appendix The following shows symbols used in flag change tables: Flag unchanged Flag changed Undefined Reset Low-order 4 bits (V, C, N, Z) of PSW are collectively called “flags”. Extension arithmetic unit register set Each of the extension arithmetic units has the following dedicated registers to store high-speed multiply and multiply and accumulate results: MDRQ Multiply Register...
Page 493 Chapter 16 Appendix Detailed description of extension instructions PUTX (high-speed multiply register transfer instruction) [Instruction format (macro name)] PUTX Dm [Assembler mnemonic] udf20 Dm, Dm [Operation] This instruction transfers the content of Dm to the high-speed multiply register MDRQ. [Flag changes] Flag Change Condition...
Page 494 Chapter 16 Appendix GETX (high-speed multiply register transfer instruction) [Instruction format (macro name)] GETX Dn [Assembler mnemonic] udf15 Dn, Dn [Operation] This instruction transfers the content of the high-speed multiply register MDRQ to Dn. [Flag changes] Flag Change Condition Always 0. Always 0.
Page 495 Chapter 16 Appendix GETCHX (transfer instruction of high-order 32 bits of multiply and accumulate register) [Instruction format (macro name)] GETCHX Dn [Assembler mnemonic] udf12 Dn, Dn [Operation] This instruction transfers the content of the multiply and accumulate register MCRH to Dn. The instruction places the content of the multiply and accumulate overflow detection flag register MCVF in the V flag.
Page 496 Chapter 16 Appendix GETCLX (transfer instruction of low-order 32 bits of multiply and accumulate register) [Instruction format (macro name)] GETCLX Dn [Assembler mnemonic] udf13 Dn, Dn [Operation] This instruction transfers the content of the multiply and accumulate register MCRL to Dn. The instruction places the content of the multiply and accumulate overflow detection flag register MCVF in the V flag.
Page 497 Chapter 16 Appendix CLRMAC (multiply and accumulate register clear instruction) [Instruction format (macro name)] CLRMAC [Assembler mnemonic] udf22 D0,D0 [Operation] This instruction clears the multiply and accumulate registers MCRH and MCRL. The instruction clears the multiply and accumulate overflow detection flag register MCVF. [Flag changes] Flag Change...
Page 498 Chapter 16 Appendix MULQ (signed high-speed multiply instruction: register to register) [Instruction format (macro name)] MULQ Dm, Dn [Assembler mnemonic] udf00 Dm, Dn [Operation] This instruction performs high-speed multiply operation by means of the multiplier provided in the extension arithmetic unit. The instruction multiplies the content of Dm (signed 32-bit integer: multiplicand) by the content of Dn (signed 32-bit integer: multiplier) and stores high-order 32 bits and low-order 32 bits of the 64-bit result respectively in the high-speed multiply register MDRQ and Dn.
Page 499 Chapter 16 Appendix MULQI (signed high-speed multiply instruction: immediate to register) [Instruction format (macro name)] MULQI imm, Dn [Assembler mnemonic] udf00 imm8,Dn : imm8 is sign-extended udf00 imm16,Dn : imm16 is sign-extended udf00 imm32,Dn [Operation] This instruction performs high-speed multiply operation by means of the multiplier provided in the extension arithmetic unit.
Page 500 Chapter 16 Appendix MULQU (unsigned high-speed multiply instruction: register to register) [Instruction format (macro name)] MULQU Dm, Dn [Assembler mnemonic] udf01 Dm, Dn [Operation] This instruction performs high-speed multiply operation by means of the multiplier provided in the extension arithmetic unit. The instruction multiplies the content of Dm (unsigned 32-bit integer: multiplicand) by the content of Dn (unsigned 32-bit integer: multiplier) and stores high-order 32 bits and low-order 32 bits of the 64-bit result respectively in the high-speed multiply register MDRQ and Dn.
Page 501 Chapter 16 Appendix MULQIU (unsigned high-speed multiply instruction: immediate to register) [Instruction format (macro name)] MULQIU imm, Dn [Assembler mnemonic] udfu01 imm8,Dn : imm8 is 0-extended udfu01 imm16,Dn : imm16 is 0-extended udfu01 imm32,Dn [Operation] This instruction performs high-speed multiply operation by means of the multiplier provided in the extension arithmetic unit.
Page 502 Chapter 16 Appendix MAC (signed multiply and accumulate instruction: register to register) [Instruction format (macro name)] MAC Dm, Dn [Assembler mnemonic] udf28 Dm, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in the extension arithmetic unit.
Page 503 Chapter 16 Appendix MACI (signed multiply and accumulate instruction: immediate to register) [Instruction format (macro name)] MACI imm, Dn [Assembler mnemonic] udf28 imm8, Dn : imm8 is sign-extended udf28 imm16, Dn : imm16 is sign-extended udf28 imm32, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in the extension arithmetic unit.
Page 504 Chapter 16 Appendix MACH (signed halfword data multiply and accumulate instruction: register to register) [Instruction format (macro name)] MACH Dm, Dn [Assembler mnemonic] udf30 Dm, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in the extension arithmetic unit.
Page 505 Chapter 16 Appendix MACIH (signed halfword data multiply and accumulate instruction: immediate to register) [Instruction format (macro name)] MACIH imm, Dn [Assembler mnemonic] udf30 imm8, Dn : imm8 is sign-extended udf30 imm16, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and adder provided in the extension arithmetic unit.
Page 506 Chapter 16 Appendix MACB (signed byte data multiply and accumulate instruction: register to register) [Instruction format (macro name)] MACB Dm, Dn [Assembler mnemonic] udf32 Dm, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in the extension arithmetic unit.
Page 507 Chapter 16 Appendix MACIB (signed byte data multiply and accumulate instruction: immediate to register) [Instruction format (macro name)] MACIB imm, Dn [Assembler mnemonic] udf32 imm8, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in the extension arithmetic unit.
Page 508 Chapter 16 Appendix MACU (unsigned multiply and accumulate instruction: register to register) [Instruction format (macro name)] MACU Dm, Dn [Assembler mnemonic] udf29 Dm, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in the extension arithmetic unit.
Page 509 Chapter 16 Appendix MACIU (unsigned multiply and accumulate instruction: immediate to register) [Instruction format (macro name)] MACIU imm, Dn [Assembler mnemonic] udfu29 imm8, Dn : imm8 is 0-extended udfu29 imm16, Dn : imm16 is 0-extended udfu29 imm32, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in the extension arithmetic unit.
Page 510 Chapter 16 Appendix MACHU (unsigned halfword data multiply and accumulate instruction: register to register) [Instruction format (macro name)] MACHU Dm, Dn [Assembler mnemonic] udf31 Dm, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in the extension arithmetic unit.
Page 511 Chapter 16 Appendix MACIHU (unsigned halfword data multiply and accumulate instruction: immediate to register) [Instruction format (macro name)] MACIHU imm, Dn [Assembler mnemonic] udfu31 imm8, Dn : imm8 is 0-extended udfu31 imm16, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and adder provided in the extension arithmetic unit.
Page 512 Chapter 16 Appendix MACBU (unsigned byte data multiply and accumulate instruction: register to register) [Instruction format (macro name)] MACBU Dm, Dn [Assembler mnemonic] udf33 Dm, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in the extension arithmetic unit.
Page 513 Chapter 16 Appendix MACIBU (unsigned byte data multiply and accumulate instruction: immediate to register) [Instruction format (macro name)] MACIBU imm, Dn [Assembler mnemonic] udfu33 imm8, Dn [Operation] This instruction performs multiply and accumulate operation by means of the multiplier and the adder provided in the extension arithmetic unit.
Page 514 Chapter 16 Appendix SAT16(16-bit saturation instruction) [Instruction format (macro name)] SAT16 imm, Dn [Assembler mnemonic] udf04 Dm, Dn [Operation] This instruction stores the 16-bit signed positive maximum value (0x00007fff) and the 16-bit signed negative maximum value (0xffff8000) in Dn respectively when Dm is equal to or greater than the positive maximum value (0x00007fff) and equal to or smaller than the negative maximum value (0xffff8000).
Page 515 Chapter 16 Appendix SAT24 (24-bit saturation instruction) [Instruction format (macro name)] SAT24 Dm, Dn [Assembler mnemonic] udf05 Dm, Dn [Operation] This instruction stores the 24-bit signed positive maximum value (0x007fffff) and the 24-bit signed negative maximum value (0xff800000) in Dn respectively when Dm is equal to or greater than the positive maximum value (0x007fffff) and equal to or smaller than the negative maximum value (0xff800000).
Page 516 Chapter 16 Appendix MCST (8-, 16- and 32-bit saturation instructions for multiply and accumulate result) [Instruction format (macro name)] MCST32, MCST16, MCST8 [Assembler mnemonic] udf02 Dm, Dn udf02 imm8, Dn : Only 0x20, 0x10 and 0x08 of the imm8 value are valid [Operation] This instruction places the content of the multiply and accumulate overflow detection flag register MCVF in the V flag.
Page 517 Chapter 16 Appendix MCST9 (9-bit saturation and positive-valuing instruction for multiply and accumulate result) [Instruction format (macro name)] MCST9 Dn, Dn [Assembler mnemonic] udf03 Dn, Dn [Operation] This instruction stores the positive maximum value (0xff) and “0” (0x00) in Dn respectively when the 32-bit multiply and accumulate result, stored in the multiply and accumulate register MCRL, is equal to or greater than the 9-bit signed positive maximum value (0x000000ff) and equal to or smaller than the 32-bit signed negative value (0x00000000).
Page 518 Chapter 16 Appendix MCST48 (48-bit saturation instruction for multiply and accumulate result) [Instruction format (macro name)] MCST48 Dn, Dn [Assembler mnemonic] udf06 Dn, Dn [Operation] This instruction stores the 48-bit signed positive maximum value (0x00007fffffffffffff ) and the negative maximum value (0xffff 800000000000) in Dn respectively when the 64-bit multiply and accumulate result, stored in the multiply and accumulate registers MCRH and MCRL, is equal to or greater than the 48-bit positive maximum value (0x00007fffffffffff ) and equal to or smaller than the negative maximum value (0xffff800000000000).
Page 519 Chapter 16 Appendix BSCH (bit search instruction) [Instruction format (macro name)] BSCH Dm, Dn [Assembler mnemonic] udf07 Dm, Dn [Operation] This instruction searches 32-bit string stored in Dm starting with the bit number specified by the content of Dn - 1 in order from larger to smaller bit numbers and stores the bit number, at which the first “1”...
Page 520 Chapter 16 Appendix SWAP (instruction for bytewise exchange of high-order and low-order bytes of 4-byte data) [Instruction format (macro name)] SWAP Dm, Dn [Assembler mnemonic] udf08 Dm, Dn [Operation] This instruction swaps high-order and low-order 8 bits of each of high-order and low-order 16 bits of the content of 32-bit data stored in Dm, further swaps high-order and low-order 16 bits and stores the resultant data in Dn.
Page 521 Chapter 16 Appendix SWAPH (instruction for exchange of high-order and low-order bytes of 2-byte data) [Instruction format (macro name)] SWAPH Dm, Dn [Assembler mnemonic] udf09 Dm, Dn [Operation] This instruction exchanges bit 15 to bit 8 and bit 7 to bit 0 of Dm and also exchanges bit 32 to bit 24 and bit 23 to bit 16 and then stores the resultant data in Dn.
Page 522 Chapter 16 Appendix Precautions for extension arithmetic programming The extension arithmetic units come equipped with the following registers designed specifically to store high- speed multiply and multiply and accumulate results. 1. Precautions for describing instructions This section provides precautions for programming associated with describing, arranging and combining instructions.
Page 523 Chapter 16 Appendix Precautions for describing word/halfword data multiply and accumulate instruction and high-speed mul- tiply instruction Word/halfword data multiply and accumulate instruction and high-speed multiply instruction are executed by a common arithmetic unit. For this reason, the next high-speed multiply instruction must be activated after the previous word/halfword data multiply and accumulate instruction has completed its operation using a common arithmetic unit.
Page 524 Chapter 16 Appendix 2) Precautions for describing word/halfword data multiply and accumulate instruction and multiply and accu- mulate instruction When a word/halfword data multiply and accumulate instruction and multiply and accumulate instruction are executed continuously with the former instruction preceding the latter, the result of the word/halfword data multiply and accumulate instruction is used to execute the sequential multiply and accumulate instruction.
Page 525 Chapter 16 Appendix 3) Precautions for describing word/halfword data multiply and accumulate instruction and MCRH and MCRL access instruction When a word/halfword data multiply and accumulate instruction and MCRH and MCRL access instruction are executed, the result of the word/halfword data multiply and accumulate instruction is used to execute the MCRH and MCRL access instruction.
Page 526 Chapter 16 Appendix 4) Precautions for describing byte data multiply and accumulate instruction and multiply and accumulate instruction When a byte data multiply and accumulate instruction and multiply and accumulate instruction are executed continuously, the result of the byte data multiply and accumulate instruction is used to execute the multiply and accumulate instruction.
Page 527 Chapter 16 Appendix 5) Precautions for describing byte data multiply and accumulate instruction and MCRH and MCRL access instruction When a byte data multiply and accumulate instruction and MCRH and MCRL access instruction are executed, the result of the byte data multiply and accumulate instruction is used to execute the MCRH and MCRL access instruction.
Page 528 Chapter 16 Appendix List of Extension Instructions (Code Length, Cycle Count) Instruction Source Destination Format Code length Cycle count Remarks PUTX PUTX PUTCX GETX GETX GETCHX GETCLX CLRMAC CLRMAC Dn can be represented by 2 to 1 byte or Dn = 0 MULQ MULQ Dn can be represented by 3 to 4 bytes...
Page 529: Special Function Registers List
Chapter 16 Appendix 16.5 Special Function Registers List Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page IVAR0...
Page 530 Chapter 16 Appendix Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x00008964 G25ICR V-29 0x00008968 G26ICR...
Page 531 Chapter 16 Appendix Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x0000A047 P7PLU P73R P72R VII-25...
Page 532 Chapter 16 Appendix Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x0000A1A1 TM5MD VIII-23 0x0000A1A4 TM6MD VIII-24...
Page 533 Chapter 16 Appendix Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page 0x0000A22C TM9CB IX-18 CB15 CB14...
Page 534 Chapter 16 Appendix Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page TCPB TCPB TCPB TCPB TCPB...
Page 535 Chapter 16 Appendix Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page AN1BUF0 AN1BU AN1BU AN1BU AN1BU...
Page 536 Chapter 16 Appendix Address Register Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Page DT63 DT62 DT61 DT60 DT59...
Page 537 Chapter 16 Appendix Special Function Registers List XVI - 85...
Page 538 Record of Changes MN103SA7D/A7G LSI User's Manual Record of Changes from the 1st Edition 1st Printing dated in April, 2006 to the 1st Edition 2nd Printing dated in February, 2008. Page Section Definition Previous Edition (Ver.1.1) New Edition (Ver.1.2) Timer17 Change - Interval timer, Timer pulse output, Event - Interval timer, Timer pulse output, Event...
Page 539 Page Section Definition Previous Edition (Ver.1.1) New Edition (Ver.1.2) II-19 Table Change 2.6.2 Address Address x'0000800X IVAR3 IVAR2 IVAR1 x'0000800X IVAR3 IVAR2 IVAR1 x'0000801X IVAR6 IVAR5 x'0000801X IVAR6 IVAR5 x'0000804X x'0000804X x'0000807X ROMCTR x'0000807X ROMCTR x'0000820X RSTCTR x'0000820X RSTCTR x'0000828X x'0000828X x'0000890X G3ICR...
Page 540 Page Section Definition Previous Edition (Ver.1.1) New Edition (Ver.1.2) V-22 Change G12IE2 Timer13 compare/capture B interrupt G12IE2 Timer13 compare B interrupt 10,9,6,5, enable flag enable flag G12IE1 Timer13 compare/capture A interrupt G12IE1 Timer13 compare A interrupt enable flag enable flag G12IR2 Timer13 compare/capture B interrupt G12IR2 Timer13 compare B interrupt request flag...
Page 541 Page Section Definition Previous Edition (Ver.1.1) New Edition (Ver.1.2) XII-14 Figure Change On pin) BOn pin) 12.3.3 nsfer bit sfer bit nter nter BnTB) BnTB) CnTIRQ) CnTIRQ) Figure Change In pin) 12.3.4 sfer bit sfer bit nter nRBSY nRBSY rrupt errupt CnRIRQ) CnRIRQ)
Page 542 Page Section Definition Previous Edition (Ver.1.1) New Edition (Ver.1.2) XIII-3 Figure Change 13.1.1 Read/Write Read/Write SWAP MSB<->LSB SC2DIR SWAP MSB<->LSB SC2DIR Reception Transmission Reception Transmission buffer buffer data buffer data buffer Start condition SC2TB SC2RB Start condition SC2TB SC2RB detection circuit detection circuit SC2STE SC2CMD SC2STE SC2CMD...
Page 543 Page Section Definition Previous Edition (Ver.1.1) New Edition (Ver.1.2) XIII Continu Change Continuous Communication Continuous Transmission This serial is equipped with a continuous com- This serial is equipped with a continuous trans- Transmis- munication function..data is loaded to the mission function.
Page 544 Page Section Definition Previous Edition (Ver.1.1) New Edition (Ver.1.2) XIII Figure Change 13.3.11 r bit Figure Change 13.3.12 er bit XIII Trans- Change In order to operate transmission and reception As data is received at the opposite edge ... so mission ...
Page 545 Page Section Definition Previous Edition (Ver.1.1) New Edition (Ver.1.2) XIII Figure Change 13.3.19 SBO2 pin SBO2 pin Tmax=2.5T SC2TBSY SC2TBSY (Data set in SC2TB) (Data set in SC2TB) Interrupt(SC2TIRQ) Interrupt(SC2TIRQ) Table Change 14.1.1 Numbers of analog input pins Max. 10 pins Numbers of analog input pins Max.
Page 546 Page Section Definition Previous Edition (Ver.1.1) New Edition (Ver.1.2) A/D2 Deletion A/D2 Conversion Data Buffer 0 Conver- sion Data Buffer 0 A/D2 Deletion A/D2 Conversion Data Buffer 1 Conver- sion Data Buffer 1 Table Change Start Trigger ANnTRG Start Trigger ANnTRGB 14.3.3 (ANnCTR0)
Page 547 MN103SA7D/A7G LSI User's Manual Record of Changes from the 1st Edition dated in March, 2005 to the 1st Edition 1st Printing dated in April, 2006. Page Section Definition Previous Edition (Ver.1) New Edition (Ver.1.1) Line 29 Change External interrupt 8 pins External interrupt 9 pins 8-18...
Page 548 Page Section Definition Previous Edition (Ver.1) New Edition (Ver.1.1) 9-25 Upper Change table TMXF - TMTGE TMONE TMCLE TMXF - TMTGE TMONE TMCLE 9-38 Table Change Set the compare/capture register Set the compare/capture register Setup TM8CA(0x0000A208)=0x09C3 TM8CA(0x0000A208)=0x0EA5 Proce- dure (2) ⋅⋅⋅...
Page 549 Page Section Definition Previous Edition (Ver.1) New Edition (Ver.1.1) 9-67 Table Change Set the count cycle Set the count cycle Setup TM8CA(0x0000A208)=0x4E1F TM8CA(0x0000A208)=0x752F Proce- dure (2) ⋅⋅⋅ Due to 20000 counts, the setting ⋅⋅⋅ Due to 30000 counts, the setting Descrip- Change tion(2)
Page 551 Colophon MN103SA7D/A7G LSI User’s Manual February, 2008 1st Edition 2nd Printing Issued by Matsushita Electric Industrial Co., Ltd.  Matsushita Electric Industrial Co., Ltd.
Page 552  Hong Kong Sales Office: Tel:49-89-46159-119 Fax:49-89-46159-195 Panasonic Semiconductor Sales (China) [PSCSCH]  Panasonic Shun Hing Industrial Sales (Hong Kong) Co., Ltd. ASIA Semiconductor Group Level 33, Office Tower, Langham Place, 8 Argyle Street,  Singapore Sales Office: Mongkok, Kowloon, Hong Kong...

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Mn103sa7d Mn103sa7g

Panasonic MN103S User Manual

Chapter 1 Overview

Chapter 2 CPU Basics

Chapter 3 Clock Generator

Chapter 4 Bus Controller

Chapter 5 Interrupt Controller

Chapter 6 ROM Correction

Chapter 7 I/O Port

Chapter 8 8-Bit Timer 8

Chapter 9 16-Bit Timer

Chapter 10 Motor Control PWM

Chapter 11 Watchdog Timer

Chapter 12 Serial Interface 0 and 1

Chapter 13 Serial Interface 2

Chapter 14 A/D Converter

Chapter 15 Regulator

Chapter 16 Appendix

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Summary of Contents for Panasonic MN103S