Panasonic MN101L Series User Manual page 488

Chapter 16
A/D Converter (ADC)
16.3.1 Setup
Input Pins of A/D Conversion Setup
Input pins for ADC is selected by the ANCTR1.ANCHS2-0.
A/D Conversion Clock Setup
The A/D conversion clock is set by the ANCTR0.ANCK2-0.
Set the A/D conversion cycle (T
(HCLK, SCLK, SYSCLK) and the A/D conversion cycle (T
ANCK2-0
A/D Conversion Sample hold Time (T
The sample hold time of A/D conversion is set with the ANCTR0.ANSH1-0.
The sample hold time of A/D conversion depends on the external circuit, so set the appropriate value based on the
analog input impedance.
Table:16.3.2 Sample Hold Time of A/D Conversion and A/D Conversion Time
XVI - 10 Operation
) between 750 ns and 100 µs. Table:16.3.1 shows the machine clock
ADCLK
Table:16.3.1 A/D Conversion Clock and A/D Conversion Cycle
A/D
conversion clock
000 SYSCLK/2
001 SYSCLK/3
010 SYSCLK/4
011 SYSCLK/6
100 SYSCLK/8
101 SYSCLK/12
110 SYSCLK/16
111 SCLK
Sample hold
ANSH1-0
clock
T
00
ADCLK
T
01
ADCLK
T
10
ADCLK
11
). (calculated as f
ADCLK
A/D conversion cycle (T
f = 10 MHz
HCLK
400 ns
(Setting is prohibited.)
600 ns
(Setting is prohibited.)
800 ns
1.2 µs
1.6 ns
2.4 µs
3.2 µs
-
) Setup
S
A/D conversion cycle (T
× 2 × (18 + 2) + 3 × 1 / f
T
ADCLK
× 6 × (18 + 6) + 3 × 1 / f
T
ADCLK
× 18 × (18 + 18) + 3 × 1 / f
T
ADCLK
-
= f
SYSCLK HCLK
)
ADCLK
f = 32.768 kHz
SCLK
61.035 µs
91.552 µs
122.070 µs
(Setting is prohibited.)
183.105 µs
(Setting is prohibited.)
244.140 µs
(Setting is prohibited.)
366.210 µs
(Setting is prohibited.)
488.281 µs
(Setting is prohibited.)
30.517 µs
)
AD
SYSCLK
SYSCLK
SYSCLK
-
/2, f )
SCLK