Panasonic MN101L Series User Manual page 238

Chapter 7
I/O Port
Register
Bit name
*1 When serial data is output, set the P5DIR.P5DIR2 to "1".
*2 When serial data is input and output, set the bit to "1".
*1 When the LSI is the master of Clock-synchronous communication, set the P5DIR.P5DIR3 to "1".
Register
Bit name
*1 When the LSI outputs the chip select signal, set the P5DIR.P5DIR4 to "1".
Register LCCTR2
Bit name SEGSL14 KEYI1EN KEY1SEL
VII - 50 Port 5
Table:7.9.4 P52 Function Selection
LCCTR2
SEGSL17 SC3SBOS
1 -
1 (*1)
0
0
Table:7.9.5 P53 Function Selection
Register LCCTR2
Bit name SEGSL16
1
0
Table:7.9.6 P54 Function Selection
LCCTR2 KEYIEN
SEGSL15 KEYI0EN
1 -
1
0
0
Table:7.9.7 P55 Function Selection
KEYIEN KEYSEL
1 - -
1 1
0
0 -
Setup
SC3MD1
SC3SBIS SC3IOM
-
- (*2) - (*2)
1
0
Setup
SC3MD1 SC23SEL
SC3SBTS SC3SEL2
- -
1 (*1) 1
0 -
Setup
KEYSEL SC3MD2
SC3SBCS
KEY0SEL
EN
- -
1 0
1 (*1)
-
0
Setup
TMIOEN0 TM1MD
TM1OEN TM1CK1-0
- -
0 Other than 11
1 Other than 11
11
0
Other than 11
SC23SEL
SC3SEL1
- -
1
1 1
0 -
Function
SEG16
SBT3B/SCL3B
P53
Function
SC23SEL
SC3SEL3
- SEG15
- KEY0B
1 SBCS3B
- P54
TMIOSEL0
TM1IOSEL
-
-
0 TM1IO (output)
0
-
Function
SEG17
SBO3B/
SDA3B
P52
Function
SEG14
KEY1B
TM1IO (input)
P55