Panasonic MN101L Series User Manual page 323

Capture Count Timing with a Trigger of Both Edges of External Interrupt Signal
Count
clock
TMnEN
bit
Compare
register
Binary
N 0000 0001
counter
External
interrupt m
input signal
Capture
trigger
Capture
register
Figure:9.8.1 Capture Count Timing with a Trigger of External Interrupt Signal
A capture trigger is generated at the both edges of the external interrupt m input signal. Synchronizing with this
capture trigger, the value of binary counter is loaded to the input capture register.
The value loaded to the capture register is the binary counter value at the falling edge of the capture trigger. When
the specified edge is selected as the capture trigger source, the capture trigger is generated only at the specified
edge of the interrupt signal. The other count timing is the same as that of the timer operation.
When the binary counter is used as a free-run counter which counts from "0x0000" to
"0xFFFF", set Compare register 1 to "0xFFFF", or set the TMnMD2.TMnBCR to "0".
.. ..
Even if an event occurs before the value of the input capture register is read out, the value of
the input capture register is rewritten.
.. ..
A capture trigger signal is generated by sampling the external interrupt input signal at the
capture clock.
Therefore, the edge of the external interrupt input signal may not be detected when an inter-
..
val of interrupt input signal is shorter than capture clock cycle.
..
N
0111 0112 0113 0114
0000 0111
5555 5556 5557 5558
0114
5555
16-bit Timer Capture Function
Chapter 9
16-bit Timer
N-1 N
5558
IX - 41