Panasonic MN101L Series User Manual page 404

Chapter 13
Serial Interface
SCIFn (n = 2, 3) Mode Register 2 (SC2MD2, SC3MD2)
bp 7
Bit name SCnFDC1
Initial value 0
Access R/W
bp
7-6 SCnFDC1-0
5 SCnRSTN
4
3 SCnCKPH
SCnSBCSE
2
1 SCnSBCSLV
0
XIII - 16 Control Registers
6
SCnFDC0 SCnRSTN
0
R/W R/W
Bit name
Output level selection after the final bit of SBOn is transmitted
00: Fixed at "1" (High) output
01: Hold the final data
10: Fixed at "0" (Low) output
11: Setting prohibit
Serial reset control
0:Reset
1:Reset release
- "0" is always read out.
Clock phase selection
(Selectable only in Clock-Synchronous communication,
always set "0" in IIC communication.)
0: Data transmission at leading edge, data reception at trailing edge
1: Data reception at leading edge, data transmission at trailing edge
SBCSn function selection
(Selectable only in Clock-Synchronous communication,
always set "0" in IIC communication.)
N
0: Disabled
1: Enabled (Chip select I/O)
SBCSn polarity selection
(Selectable only in Clock-Synchronous communication, and always set "0" in IIC
communication.)
0: Active-low
1: Active-high
- "0" is always read out.
5 4 3
- SCnCKPH SCnSBCSEN SCnSBCSLV
0 0 0
R R/W
Description
2 1
0 0
R/W R/W
0
-
0
R