3.1.1
Block Diagram
7
6
IM1
MIE
IRQLVL
2-0
PSW
5
4
3
2
1
0
IM0
level
deter-
mination
IRQNMI
Figure:3.1.1 Interrupt Block Diagram
Interrupt
CPU
7
6
5
4
3
2
1
NMICR
Undefined
Instruction
7
6
5
4
3
2
LV1-0
IRQ0ICR
0
1
DEC
2
7
6
5
4
3
2
PERI0ICR
LV1-0
0
1
DEC
2
7
6
5
4
3
2
PERI1ICR
LV1-0
0
1
DEC
2
Vector 1
0
WDTOVF
Vector 2
1
0
IE
IR
External interrupt 0
Vector N
Group-0 interrupt
Vector 29
1
0
Vector 30
Group-1 interrupt
1
0
Chapter 3
Interrupts
Overview
III - 3