Panasonic MN101L Series User Manual page 557

Details of revision from Ver.1.3 to Ver.1.4 in MN101LR05D/04D/03D/02D LSI User's Manual is shown below.
According to the details of revision, "Definition" of the table below is classified into seven groups.
Revision concerning descriptions in LSI User's Manual:
Writing error correction / Description change / Description addition / Description deletion
Revision concerning LSI specifications:
Specification change / Specification addition / Specification deletion
Modification (Ver.1.4)
Page Title Line
I-25 C. DC Char- C10
acteristics
C11
C14
IV-12 Figure:4.1.2
IV-30 Setting
Example of ...
VII-56 Table:7.11.5
Definition
Specification addition
Description change
to
- Writing error correction //Set the Clock mode Control Register
- Writing error correction CPU outage in voltage transition: 16/
- Writing error correction Setup
Ver.1.3
-
C10 I to C13 I
DD10 DD13
CLKMD.bit6-4 = 100
= 32.768 kHz, 488 µs)
f (f
SCLK SCLK
Function
LCCTR0 LCDSEL
SEGSL0 COMSL4
1 1 COM4
1 0 SEG0
1 0 TM5IO(output)
1 0 TM5IO(input)
1 0 P73
Details of Revision
Ver.1.4
Supply current in HALT
MIN: - TYP: 0.2 µA MAX: 0.4 µA
I
DD10
C11 I to C14 I
DD11 DD14
//Set the Clock mode Control Register
CLKMD.bit6-4 = 010
CPU outage in voltage transition: 32/
= 32.768 kHz, 977 µs)
f (f
SCLK SCLK
Setup
LCCTR0 LCDSEL
SEGSL0 COMSL4
1 1
1 0
0 -
0 -
0 -
<Record of Changes - 2>
Function
COM4
SEG0
TM5IO(output)
TM5IO(input)
P73