Operation - Panasonic MN101L Series User Manual

13.3.2

Operation

Initialization (Serial Reset)
SCIFn has a built-in serial reset function for abnormal operation.
Registers other than TXBUFn must be changed during the serial reset of SCIFn.
The way of serial reset is as follows.
SCIFn (n = 0, 1): SCnMD2.SCnBRKF and SCnSTR are initialized by setting SCnMD3.SCnRSTN to "0".
SCIFn (n = 2, 3): SCnSTR and SCnIICSTR are initialized by setting SCnMD2.SC3RSTN to "0".
Pin Settings
(1) To use the data pins (SBOn/SBIn), the following settings are required.
<2-wire communication>
At data reception: Set SCnMD1.SCnSBIS to "1" and SCnMD1.SCnSBOS to "0".
At data transmission: Set SCnMD1.SCnSBIS to "0" and SCnMD1.SCnSBOS to "1".
<3-wire communication>
Set SCnMD1.SCnSBIS and SCnMD1.SCnSBOS to "1". (SCnIOM must be set to "0".)
(2) To use the clock pin (SBTn), the following setting is required.
At master (SCnMD1.SCnMST is "1"): the communication clock outputs from SBTn.
At slave (SCnMD1.SCnMST is "0"): input the communication clock to SBTn.
(3) In 4-wire communication, the following setting of the chip select pin (SBCSn) is required.
SCIFn (n = 0, 1): Set SCnMD3.SCnSBCSEN to "1" and select the direction SCnMD3.SCnSBCSLV.
SCIFn (n = 2, 3): Set SCnMD2.SCnSBCSEN to "1" and select the direction SCnMD2.SCnSBCSLV.
When the LSI is a master, the chip select signal outputs from SBCSn.
When the LSI is a slave, the input signal to SBTn is masked and SBOn is high impedance state while chip
select signal input to SBCSn is negated.
In time-division 2-wire communication with SBOn, be careful to prevent data collision at
SBOn.
.. ..
When the LSI only send data (not receive data), set SCnMD1.SCnSBIS to "0".
When the LSI only receive data (not send data), set SCnMD1.SCnSBOS to "0".
.. ..
Clock-Synchronous Communication
Chapter 13
Serial Interface
XIII - 29