Panasonic MN101L Series User Manual page 359

Count Timing of Timer Operation (Time Base Timer)
The counter counts up with the selected clock source as a counter clock.
14 13 12 11 10
15 14 13 12
1/2 1/2 1/2 1/2
Figure:10.4.1 Count Timing of Timer Operation (Time Base Timer)
• When the selected interrupt cycle elapsed, the time base interrupt request (PERI0DT2) of the
group 0 interrupt factor register (PERI0DT)
Stop the timer when switching the count clock. If the count clock is changed during counting,
the timer doesn't count correctly.
.. ..
The timer can be initialized by writing an arbitrary value to the time base timer clear control
register (TBCLR).
.. ..
9 8 7 6 5 4
10 9 8 7
1/2 1/2 1/2 1/2
is set to "1".
3 2 1 0
MUX
General-Purpose Time Base/Free-Running Timer
peripheral function
Time Base Timer
Chapter 10
f
HCLK
f
SCLK
X - 13