Setup Example - Panasonic MN101L Series User Manual

Chapter 9
16-bit Timer
In the initial state after releasing reset, the timer pulse output is reset and fixed to "Low".
Therefore, release the reset of the timer pulse output by setting the TMnMD1.TMnCL to "0".
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Regardless of whether TMnBC is stopped or in active, the timer output becomes "Low", when
the TMnMD1.TMnCL is set to "1".
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Release the reset of the timer pulse output when the timer count is stopped.
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9.5.2

Setup Example

Timer Pulse Output Setup Example
Here is an example that, using Timer 7, a 50 kHz pulse is output from TM7IOA pin. In order to output a 50 kHz
pulse, select HCLK for clock source, and set 1/2 cycle (100 kHz) in the Timer 7 compare register.
HCLK (at f = 8 MHz) is selected as a clock source.
HCLK
The setup procedure and its description are shown below.
Step Setting
1 Disable the timer counter
2 Select the timer output pin
3
4 Set the timer mode register
5
6
7
Set the output cycle
8
9 Enable the timer counter
IX - 30 16-bit Timer Pulse Output
Register
TM7MD.TM7EN = 0
TMIOEN1.TM7OEN = 1
P0DIR.P0DIR4 = 1
TM7MD2.TM7PWM = 0
TM7MD2.TM7BCR = 1
TM7MD1.TM7CL = 0
TM7MD1.TM7CK1-0 = 00
TM7MD1.TM7PS1-0 = 00
TM7PR1 = 0x004F
TM7MD1.TM7EN = 1
Description
Disable the timer count operation.
Select the timer output pin.
[Chapter 7 I/O Port]
Select the timer output.
Select the TM7BC clear source.
Enable the timer output.
Select HCLK as the count clock source.
Set the timer output cycle.
Setup value: 80 - 1 = 79 (0x004F)
Enable the timer count operation.