Clock Configuration; Two Devices Down Card Topology; Hot-Plug Clock Topology - Intel Pentium M Processor Design Manual

Figure 89.

Two Devices Down Card Topology

Table 69. Two Devices Down Length Requirements
Configuration
100 MHz PCI-X
8.1.6

Clock Configuration

All PCI clocks must be disabled in the BIOS for any unused/unpopulated PCI/PCI-X slots. The
PxPCLKO[5:0] pins may each be disabled by writing to the Disable PCLKOUT 5 – 0 bits
(DPCLK, bits 15:10, configuration register offset 40h in each bridge). These clocks function the
same in serial and dual-slot parallel modes. In serial mode, the PxPCLKO[5:0] signals are all
driven low when the clock to the slot is disabled by the Hot-Plug controller, regardless of the
DPCLK bits. Once the Hot-Plug controller connects the clock to the slot, these clocks are enabled
again—which clocks are enabled does depend on DPCLK at this point. It is expected that
PxPCLK0 may be connected to the PCI slot in single-slot parallel mode.
Figure 90.

Hot-Plug Clock Topology

Table 70. Hot-Plug Clock Routing Length Parameters
Clock Speed
66 MHz
100 MHz
133 MHz
Design Guide
®
Intel Pentium
Intel
P64H2
Intel
Lower
3.5" – 7.0"
®
Intel L1
P64H2
L1 (inches)
0.25 – 1.0
3.5 – 4.5
1.5 – 2.5
®
M Processor and Intel
P64H2 to
Dev ice
®
P64H2 to
Dev ice
®
P64H2 to Device
Upper
3.5" – 7.0"
Ω
33 L2
L2 (inches)
(L – L3) – 2.523
fbi
0.25 – 0.5 = L3
0.5 – 1.0 = L3
®
E7501 Chipset Platform
®
Intel 82870P2 (Intel P64H2)
Dev ice
Dev ice
Slot
L3
Switch
L3 (inches)
0.75 – 1.25
0.25 – 0.5 = L2
0.5 – 1.0 = L2
129