Package C-State Power Specifications; System Memory Power Management - Intel Xeon Processor E5-1600 Datasheet

Power Management
• Additional power savings actions, as allowed by the exit latency requirements,
include putting Intel QPI and PCIe* links in L1, the uncore is not available, further
voltage reduction can be taken.
In package C6 state, all cores have saved their architectural state and have had their
core voltages reduced to zero volts. The LLC retains context, but no accesses can be
made to the LLC in this state, the cores must break out to the internal state package C2
for snoops to occur.
4.2.6

Package C-State Power Specifications

The table below lists the processor package C-state power specifications for various
processor SKUs.
Table 4-10. Package C-State Power Specifications
TDP SKUs
8-Core / 6-Core
150W (8-core)
135W (8-core)
130W (8-core)
130W (6-core)
130W (6-core 1S WS)
115W (8-core)
95W (8-core)
95W (6-core)
70W (8-core)
60W (6-core)
LV95W-8C (8-core)
LV70W-8C (8-core)
4-Core / 2-Core
130W (4-core)
130W (4-Core 1S WS)
95W (4-core)
80W (4-core)
80W (2-core)
Notes:
1. Package C1E power specified at Tcase = 60°C.
2. Package C3/C6 power specified at Tcase = 50°C.
4.3

System Memory Power Management

The DDR3 power states can be summarized as the following:
• Normal operation (highest power consumption).
Intel® Xeon® Processor E5-1600/E5-2600/E5-4600 Product Families
Datasheet Volume One
C1E (W) C3 (W)
58
47
47
53
53
47
47
35 (E5-2660)
48
35 (E5-2620)
39
38
47
39
53
53
47
42
30 (E5-2603)
42
C6 (W)
27 15
22 15
22 15
35 21
35 21
22 15
22 15
22 15
21 (E5-2620)
20 14
20 14
22 15
20 14
28 16
28 16
22 15
21 16
30 21
97