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DMA channel useburst set register (DMA_CHNL_USEBURST_SET) ....................... 172
DMA channel useburst clear register (DMA_CHNL_USEBURST_CLR) .................... 172
DMA channel request mask set register (DMA_CHNL_REQ_MASK_SET) ................ 173
DMA channel request mask clear register (DMA_CHNL_REQ_MASK_CLR) .............. 174
DMA channel enable set register (DMA_CHNL_ENABLE_SET) ............................ 174
DMA channel enable clear register (DMA_CHNL_ENABLE_CLR) ......................... 175
DMA channel primary-alternate set register (DMA_CHNL_PRI_ALT_SET) .............. 175
DMA channel primary-alternate clear register (DMA_CHNL_PRI_ALT _CLR) .......... 176
DMA channel priority set register (DMA_CHNL_PRIORITY_SET) ......................... 176
DMA channel priority clear register (DMA_CHNL_PRIORITY_CLR) ...................... 177
DMA bus error clear register (DMA_ERR_CLR) .............................................. 177
19.5
Register map ............................................................................... 179
20 Analog-to-digital converter (ADC) ............................................................... 180
20.1
Introduction ................................................................................ 180
20.2
Features .................................................................................... 180
20.3
Functional description ................................................................... 181
Operation ADC with non-interrupt ........................................................... 181
Operation ADC with interrupt ................................................................. 183
20.4
Registers (Base address : 0x4100_0000) ............................................... 183
ADC control register (ADC_CTR) .............................................................. 183
ADC channel select register (ADC_CHSEL) .................................................. 184
ADC start register (ADC_START) .............................................................. 185
ADC conversion data register (ADC_DATA) .................................................. 185
ADC Interrupt register (ADC_INT) ............................................................ 185
ADC Interrupt Clear register (ADC_INTCLR) ................................................ 186
20.5
Register map ............................................................................... 187
21 Pulse-Width Modulation (PWM) ................................................................... 188
21.1
Introduction ................................................................................ 188
21.2
Features .................................................................................... 188
21.3
Functional description ................................................................... 189
Timer/Counter control ......................................................................... 189
Timer/Counter ................................................................................... 189
PWM mode ....................................................................................... 193
Interrupt.... ...................................................................................... 194
Dead zone generation .......................................................................... 195
Capture event ................................................................................... 196
How to set the PWM ............................................................................ 198
21.4
PWM Channel-0 Registers (Base address : 0x4000_5000) ........................... 198
Channel-0 interrupt register(PWMCH0IR) ................................................... 198
W7500x Reference Manual Version1.1.0
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