Dma Channel Primary-Alternate Clear Register (Dma_Chnl_Pri_Alt; Dma Channel Priority Set Register (Dma_Chnl_Priority_Set) - Wiznet W7500 Reference Manual

This read/write register configure a DMA channel to use the alternate data structure.
Reading the register returns the status of which data structure is in use for the
corresponding DMA channel.
Read as :
0 – DMA Channel [Channel-1] is using the primary data structure.
1 – DMA Channel [Channel-1] is using the alternate data structure.
Write as :
0 – No effect. Use the CHNL_PRI_ALT _CLR register to set bit [Channel-1] to 0
1 – Selects the alternate data structure for channel [Channel-1]
DMA channel primary-alternate clear register
(DMA_CHNL_PRI_ALT _CLR)
Address offset : 0x034
Reset value : -
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res res res res
15 14 13 12
res res res res
[Channel-1] CHNL_PRI_ALT_CLR – Set the appropriate bit to select the primary data
structure for the corresponding DMA channel.
This write only register configures a DMA channels to use the primary data structure.
0 : No effect. Use the CHNL_PRI_ALT _SET register to select the alternate
data structure.
1 : Selects the primary data structure for channel [Channel-1]

DMA channel priority set register (DMA_CHNL_PRIORITY_SET)

Address offset : 0x038
Reset value : 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
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res res res res
11 10 9 8
res res res res
27 26 25 24
res res res res
11 10 9 8
23 22 21 20
res res res res
7 6 5 4
res res CHNL_PRI_ALT_CLR[5:0]
23 22 21 20
res res res res
7 6 5 4
19 18 17 16
res res res res
3 2 1 0
WO
19 18 17 16
res res res res
3 2 1 0
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