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12 Clock Reset generator (CRG) ........................................................................ 39
12.1
Introduction ................................................................................. 39
12.2
Features ..................................................................................... 39
Reset....... ........................................................................................ 39
Clock....... ........................................................................................ 40
12.3
Functional description .................................................................... 41
External Oscillator Clock ....................................................................... 41
RC oscillator clock ............................................................................... 42
PLL......... ......................................................................................... 42
Generated clock .................................................................................. 42
12.4
Registers (Base address : 0x4100_1000) ................................................ 44
OSC power down register (OSC_PDR) ......................................................... 44
PLL power down register (PLL_PDR) .......................................................... 44
PLL frequency calculating register (PLL_FCR) .............................................. 44
PLL output enable register (PLL_OER) ....................................................... 45
PLL bypass register (PLL_BPR) ................................................................. 45
PLL input clock source select register (PLL_IFSR) .......................................... 46
FCLK source select register (FCLK_SSR) ...................................................... 46
FCLK prescale value select register (FCLK_PVSR) .......................................... 47
SSPCLK source select register (SSPCLK_SSR) ................................................ 47
SSPCLK prescale value select register (SSPCLK_PVSR) .................................... 48
ADCCLK source select register (ADCCLK_SSR) .............................................. 48
ADCCLK prescale value select register (ADCCLK_PVSR) ................................... 48
TIMER0CLK source select register (TIMER0CLK_SSR) ....................................... 49
TIMER0CLK prescale value select register (TIMER0CLK_PVSR) ........................... 49
TIMER1CLK source select register (TIMER1CLK_SSR) ....................................... 50
TIMER1CLK prescale value select register (TIMER1CLK_PVSR) ........................... 50
PWM0CLK source select register (PWM0CLK_SSR) .......................................... 51
PWM0CLK prescale value select register (PWM0CLK_PVSR) .............................. 51
PWM1CLK source select register (PWM1CLK_SSR) .......................................... 52
PWM1CLK prescale value select register (PWM1CLK_PVSR) .............................. 52
PWM2CLK source select register (PWM2CLK_SSR) .......................................... 53
PWM2CLK prescale value select register (PWM2CLK_PVSR) .............................. 53
PWM3CLK source select register (PWM3CLK_SSR) .......................................... 54
PWM3CLK prescale value select register (PWM3CLK_PVSR) .............................. 55
PWM4CLK source select register (PWM4CLK_SSR) .......................................... 55
PWM4CLK prescale value select register (PWM4CLK_PVSR) .............................. 56
PWM5CLK source select register (PWM5CLK_SSR) .......................................... 56
PWM5CLK prescale value select register (PWM5CLK_PVSR) .............................. 57
W7500x Reference Manual Version1.1.0
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