Register Map - Wiznet W7500 Reference Manual

25.7 Register map

The following Table 35 summarizes the UART1 registers.
Offset Register
UART1DR
0x000
reset value
UART1RSR/
UART1ECR
0x004
reset value
UART1FR
0x018
reset value
0x020 UART1ILPR
reset value
0x024 UART1IBRD
reset value
0x028 UART1FBRD
reset value
0x02C UART1LCR_H
reset value
0x030 UART1CR
reset value
0x034 UART1IFLS
reset value
0x038 UART1IMSC
reset value
0x03C UART1RIS
reset value
0x040 UART1MIS
reset value
0x044 UART1ICR
reset value
W7500x Reference Manual Version1.1.0
Table 35 UART1 register map and reset values
0 0
0 0
DATA
0 0 0 0 0 0 0 0 0 0
0 0
X 1 1 0 0 0 X
ILPDVSR
0 0 0 0 0 0
BAUD DIVINT
0 0 0 0 0 0 0 0 0 0 0 0
BAUD DIVFRAC
0 0 0 0
WLEN
1 1 1 1 1 1
1 1 0 0 0 0 0
0 1 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0
비고
Data Register
0 0
Receive Status/Error Clear Register
0 0
Flage Register
X X
IrDA Low-Power Counter Register
0 0
Integer Baud Rate Register
0 0
Fractional Baud Rate Register
0 0
Line Control. Register
1 1
Control Register
0 0
Interrupt FIFO Level Select Register
1 0
Interrupt Mask Set/Clear Register
0 0
Raw Interrupt Status Register
0 0
Masked Interrupt StatusRegister
0 0
Interrupt Clear Register
0 0
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