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PWM6CLK source select register (PWM6CLK_SSR) .......................................... 57
PWM6CLK prescale value select register (PWM6CLK_PVSR) .............................. 58
PWM7CLK source select register (PWM7CLK_SSR) .......................................... 58
PWM7CLK prescale value select register (PWM7CLK_PVSR) .............................. 59
RTC High Speed source select register (RTC_HS_SSR) ..................................... 59
RTC High Speed prescale value select register (RTC_HS_PVSR) ......................... 60
RTC source select register (RTC_SSR) ........................................................ 60
WDOGCLK High Speed source select register (WDOGCLK_HS_SSR) ...................... 61
WDOGCLK clock source select register (WDOGCLK_SSR).................................. 62
UARTCLK source select register (UARTCLK_SSR) ........................................... 62
UARTCLK prescale value select register (UARTCLK_PVSR) ................................ 63
MIICLK enable control register (MIICLK_ECR) ............................................... 63
Monitoring Clock source select register (MONCLK_SSR) ................................... 64
12.5
Register map ................................................................................ 65
13 Tcp/ip core Offload Engine (TOE) .................................................................. 67
13.1
Introduction ................................................................................. 67
13.2
Features ..................................................................................... 67
13.3
Functional description .................................................................... 68
13.4
TOE Memory map ........................................................................... 68
Common register map ........................................................................... 70
Socket register map ............................................................................. 70
Memory............................................................................................. 71
13.5
Common register (Base : 0x4600_0000) ................................................ 73
VERSIONR (TOE Version Register) .............................................................. 73
TCKCNTR (Ticker Counter Register) .......................................................... 73
IR (Interrupt Register) ........................................................................... 74
IMR (Interrupt Mask Register) .................................................................. 74
IRCR (Interrupt Clear Register) ................................................................ 75
SIR (Socket Interrupt Register) ................................................................ 76
SIMR (Socket Interrupt Mask Register) ........................................................ 76
MR (Mode Register) .............................................................................. 77
PTIMER (PPP Link Control Protocol Request Timer Register) ............................. 78
PMAGICR (PPP Link Control Protocol Magic number Register) ........................... 78
PHAR (Destination Hardware Address Register in PPPoE) ................................. 78
PSIDR (Session ID Register in PPPoE) .......................................................... 79
PMRUR (Maximum Receive Unit Register in PPPoE) ........................................ 80
SHAR (Source Hardware Address Register)................................................... 80
GAR (Gateway Address) ......................................................................... 81
W7500x Reference Manual Version1.1.0
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