Interrupt And Reset Request; Watchdog Timer Registers (Base Address : 0X4000_0000); Watchdog Timer Load Register(Wdtload) - Wiznet W7500 Reference Manual

PCLK is the main APB system clock and is used by the register interface.

Interrupt and reset request

An interrupt is generated when the counter reaches 0 and is only cleared when the
interrupt clear register is accessed.
The register holds the value until the interrupt is cleared.
Reset request is asserted when the counter reaches 0 repeatedly and is not
reprogrammed.
Users can mask interrupts by writing 0 to the Interrupt Enable bit in the control register.
Users can read the following from status registers:
Raw interrupt status, before masking.
-
Final interrupt status, after masking.
-
without reprogram
Watchdog timer is
programmed

23.4 Watchdog timer Registers (Base address : 0x4000_0000)

Watchdog timer Load Register(WDTLoad)

Address offset : 0x000
Reset value : 0xFFFF_FFFF
31
[31:0] WLR – Watchdog timer Load Register.
This register contains the value from which the counter is to decrement.
When this register is written to, the count is immediately restarted from the
new value. The minimum valid value for WDTLoad is 1.
W7500x Reference Manual Version1.1.0
Count down
Counter reaches zero
If the interrupt enable bit in the
WDTControl register is set to 1,
interrupt is asserted.
Figure 41 Watchdog timer operation flow diagram
Counter reloaded
and count down
without reprotram
If the reset enable bit in the
WDTControl register is set to 1, reset
WLR
R/W
Counter reaches zero
request signal is asserted.
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