Pll Output Enable Register (Pll_Oer); Pll Bypass Register (Pll_Bpr) - Wiznet W7500 Reference Manual

15 14 13 12
res res
[1:0] OD
[13:8] N
[21:16] M
These bits are written by S/W to set frequency of PLL output.
PLL output frequency FOUT is calculated by the following equations:
FOUT = FIN x M / N x 1 / OD
Where:
M = M[5] x 32 + M[4] x 16 + M[3] x 8 + M[2] x 4 + M[1] x 2 + M[0] x 1 (2 ~ 63)
N = N[5] x 32 + N[4] x 16 + N[3] x 8 + N[2] x 4 + N[1] x 2 + N[0] x 1 (1 ~ 63)
OD = 2 ^ (2 x OD[1]) x 2 ^ (1 x OD[0])

PLL output enable register (PLL_OER)

Address offset : 0x018
Reset value : 0x0000_0001
31 30 29 28
res res res res
15 14 13 12
res res res res
[0] PLLOEN – output enable register of PLL
This bit written by S/W to control output enable of PLL
0 : Clock out is disable. VCO is working but FOUT is low only.
1 : Clock out is enable.

PLL bypass register (PLL_BPR)

Address offset : 0x01c
Reset value : 0x0000_0000
31 30 29 28
res res res res
W7500x Reference Manual Version1.1.0
11 10 9 8
N
R/W
27 26 25 24
res res res res
11 10 9 8
res res res res
27 26 25 24
res res res res
7 6 5
res res res
23 22 21
res res res
7 6 5 4
res res res res
23 22 21
res res res
R/W
4 3 2 1
res res res
20 19 18 17
res res res res
3 2 1
res res res PLLOEN
20 19 18 17
res res res res
45 / 399
0
OD
R/W
16
res
0
R/W
16
res