Timer0_0 Interrupt Clear Register (Dualtimer0_0Timerintclr); Timer0_0 Raw Interrupt Status Register (Dualtimer0_0Timerris) - Wiznet W7500 Reference Manual

[0] OC – One-shot Count
0 : Wrapping mode, default.
1 : One-shot mode.
[1] TS – Timer Size
0 : 16-bit counter, default.
1 : 32-bit counter.
[3:2] TP – Timer Prescale.
00 : 0 stages of prescale, clock is divided by 1, default.
01 : 4 stages of prescale, clock is divided by 16.
10 : 8 stages of prescale, clock is divided by 256.
11 : Undefined, do not use.
[5] IE – Interrupt Enable.
0 : Timer Interrupt disable.
1 : Timer Interrupt enabled, default.
[6] TM – Timer Mode.
0 : Timer is in free-running mode, default.
1 : Timer is in periodic mode.
[7] TE – Timer Enable.
0 : Timer disabled, default.
1 : Timer enabled.

Timer0_0 Interrupt Clear Register (DUALTIMER0_0TimerIntClr)

Base address : 0x4000_1000
Address offset : 0x0C
31 30 29 28
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15 14 13 12
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[0] TIC – Interrupt Clear
Set to this register clears the interrupt output from the counter.

Timer0_0 Raw Interrupt Status Register (DUALTIMER0_0TimerRIS)

Base address : 0x4000_1000
Address offset : 0x10
W7500x Reference Manual Version1.1.0
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21 20
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7 6 5 4
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19 18 17 16
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3 2 1 0
res res res TIC
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