Watchdog Timer Raw Interrupt Status Register (Wdtris); Watchdog Timer Masked Interrupt Status Register (Wdtmis) - Wiznet W7500 Reference Manual

W7500 series
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[0] WIC – Watchdog timer Interrupt Clear
A write of 1 to this register clears the watchdog interrupt, and reloads the
counter from the value in WDTLoad.

Watchdog timer Raw Interrupt Status Register (WDTRIS)

Address offset : 0x010
Reset value : 0x0000_0000
31
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28
res
res
res
res
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12
res
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res
[0] RIS – Watchdog timer Raw Interrupt Status.
This register indicates the raw interrupt status from the counter. This value is
ANDed with the interrupt enable bit from the control register to create the
masked interrupt, that is passed to the interrupt output pin.

Watchdog timer Masked Interrupt Status Register (WDTMIS)

Address offset : 0x014
Reset value : 0x0000_0000
31
30
29
28
res
res
res
res
15
14
13
12
res
res
res
res
[0] MIS – Watchdog timer Masked Interrupt Status.
This register indicates the masked interrupt status from the counter. This
value is the logical AND of the raw interrupt status with the interrupt
enable(IEN) bit from the control register, and is the same value that is passed
to the interrupt output pin.
W7500x Reference Manual Version1.1.0
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res
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11
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8
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res
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res
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res
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7
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3
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1
0
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RIS
R
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2
1
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MIS
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