Timer1_0 Masked Interrupt Status Register (Dualtimer1_0Timermis); Timer1_0 Background Load Register (Dualtimer1_0Timerbgload) - Wiznet W7500 Reference Manual

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[0] RIS – Raw Interrupt Status Register
This register indicates the raw interrupt status from the counter. This value
is ANDed with the timer interrupt enable bit from the Timer Control Register
to create the masked interrupt, that is passed to the interrupt output pin.
Timer1_0 Masked Interrupt Status Register
(DUALTIMER1_0TimerMIS)
Base address : 0x4000_2000
Address offset : 0x14
Reset value : 0x0000_0000
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[0] MIS – Masked Interrupt Status Register
This register indicates the masked interrupt status from the counter. This
value is the logical AND of the raw interrupt status with the timer interrupt enable bit
from the Timer Control Register, and is the same value that is passed to the interrupt
output pin.
Timer1_0 Background Load Register
(DUALTIMER1_0TimerBGLoad)
Base address : 0x4000_2000
Address offset : 0x18
Reset value : 0x0000_0000
31
[31:0] BGL – Background Load Register
W7500x Reference Manual Version1.1.0
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BGL
R/W
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