Ssp1 Interrupt Clear Register (Ssp1Icr); Ssp1 Dma Control Register, (Ssp1Dmacr) - Wiznet W7500 Reference Manual

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[0] RORMIS – Gives the receive over run masked interrupt status, after masking, of the
SSPRORINTR interrupt
[1] RTMIS – Gives the receive timeout masked interrupt state, after masking, of the
SSPRTINTR interrupt
[2] RXMIS – Gives the receive FIFO masked interrupt state, after masking, of the
SSPRXINTR interrupt
[3] TXMIS – Gives the transmit FIFO masked interrupt state, after masking, of the
SSPTXINTR interrupt

SSP1 Interrupt clear register (SSP1ICR)

Address offset: 0x0020
Reset value: 0x0000_00000
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[0] RORICS – Clears the SSPRORINTR interrupt
[1] RTIC – Clears the SSPRTINTR interrupt

SSP1 DMA control register, (SSP1DMACR)

Address offset: 0x0024
Reset value: 0x0000_00000
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W7500x Reference Manual Version1.1.0
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3 2 1 0
TXM RXM RTM ROR
IS IS IS MIS
R/W R/W R/W R/W
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ROR
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IC
R/W R/W
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