Wiznet W7500 Reference Manual page 11

Channel-2 interrupt clear register(PWMCH2ICR) .......................................... 218
Channel-2 Timer/Counter Register (PWMCH2TCR) ........................................ 218
Channel-2 Prescale Counter Register (PWMCH2PCR) ..................................... 219
Channel-2 Prescale Register (PWMCH2PR) .................................................. 219
Channel-2 Match Register (PWMCH2MR) .................................................... 220
Channel-2 Limit Register (PWMCH2LR) ...................................................... 220
Channel-2 Up-Down Mode Register (PWMCH2UDMR) ...................................... 220
Channel-2 Timer/Counter Mode Register (PWMCH2TCMR)............................... 221
Channel-2 PWM output Enable and External input Enable Register (PWMCH2PEEER)
221
Channel-2 Capture Mode Register (PWMCH2CMR) ......................................... 222
Channel-2 Capture Register (PWMCH2CR) .................................................. 222
Channel-2 Periodic Mode Register (PWMCH2PDMR) ....................................... 223
Channel-2 Dead Zone Enable Register (PWMCH2DZER) ................................... 223
Channel-2 Dead Zone Counter Register (PWMCH2DZCR) ................................. 224
21.9 Register map ............................................................................... 225
21.10 PWM Channel-3 Registers (Base address : 0x4000_5300) ........................... 226
Channel-3 interrupt register(PWMCH3IR) ................................................... 226
Channel-3 interrupt enable register(PWMCH3IER) ........................................ 226
Channel-3 interrupt clear register(PWMCH3ICR) .......................................... 227
Channel-3 Timer/Counter Register (PWMCH3TCR) ........................................ 227
Channel-3 Prescale Counter Register (PWMCH3PCR) ..................................... 228
Channel-3 Prescale Register (PWMCH3PR) .................................................. 228
Channel-3 Match Register (PWMCH3MR) .................................................... 229
Channel-3 Limit Register (PWMCH3LR) ...................................................... 229
Channel-3 Up-Down Mode Register (PWMCH3UDMR) ...................................... 230
Channel-3 Timer/Counter Mode Register (PWMCH3TCMR)............................... 230
Channel-3 PWM output Enable and External input Enable Register (PWMCH3PEEER)
231
Channel-3 Capture Mode Register (PWMCH3CMR) ......................................... 231
Channel-3 Capture Register (PWMCH3CR) .................................................. 231
Channel-3 Periodic Mode Register (PWMCH3PDMR) ....................................... 232
Channel-3 Dead Zone Enable Register (PWMCH3DZER) ................................... 232
Channel-3 Dead Zone Counter Register (PWMCH3DZCR) ................................. 233
21.11 Register map ............................................................................... 234
21.12 PWM Channel-4 Registers (Base address : 0x4000_5400) ........................... 235
Channel-4 interrupt register(PWMCH4IR) ................................................... 235
Channel-4 interrupt enable register(PWMCH4IER) ........................................ 235
Channel-4 interrupt clear register(PWMCH4ICR) .......................................... 236
W7500x Reference Manual Version1.1.0
11 / 399