Functional Description; Clock And Clock Enable; Timer Size; Prescaler - Wiznet W7500 Reference Manual

22.3 Functional description

Clock and clock enable

The dual timers contain PCLK and TIMERCLK clock inputs. PCLK is the main APB system clock
and is used by the register interface. TIMERCLK is the input to the prescale units and the
decrementing counters. PCLK and TIMERCLK are synchronous.
The dual timers consist two programmable 32-bit Free-Running Counters(FRC) which operate
independently. The two timers operate from one TIMERCLK but Each FRC is controlled
independently by individual clock enable.

Timer size

Users can select FRC as 16-bit or 32-bit using the control register.

Prescaler

The timer has a prescaler that can divide down the enabled clock rate by 1, 16 or 256.

Repetition mode

There are two repetition mode: one-shot and wrapping mode. Wrapping mode has two modes:
free-running and periodic mode.
One-shot mode
The counter generates an interrupt once. When the counter reaches 0, it halts until
users reprogram it. Users can do this as below:
Clear the one-shot count bit in the control register, in which case the count

proceeds according to the selection of wrapping mode(free-running or
periodic mode).
 Write a new value to the Load Value register.
Wrapping mode
Free-running mode
The counter wraps after reaching its zero value, and continues to count down from
the maximum value. This is the default mode.
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