Channel-7 Interrupt Clear Register(Pwmch7Icr); Channel-7 Timer/Counter Register (Pwmch7Tcr) - Wiznet W7500 Reference Manual

[0] MIE – Match Interrupt Enabled.
O : Match interrupt is not enabled.
1 : Match interrupt is enabled.
[1] OIE – Overflow Interrupt Enable.
O : Overflow interrupt is not enabled.
1 : Overflow interrupt is enabled.
[2] CIE – Capture Interrupt Enable.
O : Capture interrupt is not enabled.
1 : Capture interrupt is enabled.

Channel-7 interrupt clear register(PWMCH7ICR)

Base address : 0x4000_5700
Address offset : 0x08
31 30 29 28
res res res res
15 14 13 12
res res res res
This bit is set by software, cleared by hardware when a capture interrupt becomes 0.
[0] MIC – Match Interrupt
O : No action.
1 : Match interrupt is cleared.
[1] OIC – Overflow Interrupt
O : No action.
1 : Overflow Interrupt is cleared.
[2] CIC – Capture Interrupt Clear.
O : No action.
1 : Capture Interrupt is cleared.

Channel-7 Timer/Counter Register (PWMCH7TCR)

Base address : 0x4000_5700
Address offset : 0x0C
Reset value : 0x0000_0000
W7500x Reference Manual Version1.1.0
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21 20
res res res res
7 6 5 4
res res res res
R/W R/W R/W
19 18 17 16
res res res res
3 2 1 0
res CIC OIC MIC
W W W
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