Uart2Cr (Uart2 Control Register); Uart2Isr/Icr (Uart2 Interrupt Status/Interrupt Clear Register) - Wiznet W7500 Reference Manual

Read Only
0: The bit is set when transmit holding register is full.
1: The bit is set when transmit buffer is full.

UART2CR (UART2 Control Register)

Address offset: 0x008
Reset value: 0x0000_0000
The UART2CR is the control register.
31 30 29 28
Res Res res res
15 14 13 12
Res Res res res
[5] ROIE – Receive Overrun Interrupt Enable
[4] TOIE – Transmit Overrun Interrupt Enable
[3] RXIE – Receive Interrupt Enable
[2] TXIE – Transmit Interrupt Enable
[1] RXE – Receive enable
If this bit is set to 1, the receive section of the UART2 is enabled.
When the UART2 is disabled in the middle of reception, it completes the current
character before stopping.
[0] TXE – Transmit enable
If this bit is set to 1, the transmit section of the UART2 is enabled

UART2ISR/ICR (UART2 Interrupt Status/Interrupt Clear Register)

Address offset: 0x00C
Reset value: 0x0000_0000
The UART2ISR is the interrupt status register.
A write to the UART2ISR register clear to interrupts.
31 30 29 28
res res res res
W7500x Reference Manual Version1.1.0
27 26 25 24
res res res res
11 10 9 8
res res res res
27 26 25 24
res res res res
23 22 21 20
res res res res
7 6 5 4
res res
ROIE TOIE
R/W R/W
23 22 21 20
res res res res
19 18 17 16
res res res res
3 2 1 0
RXIE TXIE RXE TXE
R/W R/W R/W R/W
19 18 17 16
res res res res
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