Uart0Cr (Uart0 Control Register) - Wiznet W7500 Reference Manual

The parity bit is transmitted and checked as a 1 when EPS bit set '0'
The parity bit is transmitted and checked as a 0 when EPS bit set '1'
[6:5] WLEN – Word length
[4] FEN – Enable FIFO
0: The FIFO become 1-byte-deep holding register.
1: The transmit and receive FIFO buffers are enable (FIFO mode)
[3] STP2 – Two stop bit select
1: Two stop bits are transmitted at the end of the frame
[2] EPS – Even parity select
0: odd parity.
1: even parity
[1] PEN – Parity enable
0: parity is disabled and no parity bit added to the data frame
1: parity checking and generations is enabled
[0] BRK – Send break
0: For normal use, the bit must be cleared to 0
1: The low-level is continually output on the UARTTXD output
PEN EPS
0 X
1 1
1 0
1 0
1 1

UART0CR (UART0 Control register)

Address offset: 0x0030
Reset value: 0x0300
The UART0CR register is the control register
31 30 29
res res res
15 14 13
CTSEn RTSEn Out2 Out1
W7500x Reference Manual Version1.1.0
00 01
5 bits 6 bits
SPS
X
0
0
1
1
28 27 26 25
res res res res
12 11 10 9
RTS DTR RXE
10 11
7 bits 8 bits
Parity bit(Transmitted or checked)
Not transmitted or checked
Even parity
Odd parity
1
0
24 23 22 21
res res res res
8 7 6 5
res
TXE
20 19 18 17
res res res res
4 3 2 1
SIRLP SIREN
334 / 399
16
res
0
UARTEN