Direct Memory Access Controller (Dma); Introduction; Features; Functional Description - Wiznet W7500 Reference Manual

19

Direct memory access controller (DMA)

19.1 Introduction

Direct memory access (DMA) is used in order to provide high-speed data transfer between
peripherals and memory as well as memory to memory. Data can be quickly moved by DMA
without any CPU actions. This keeps CPU resources free for other operations.
The DMA controller has up to 6 channels in total, each dedicated to managing memory access
requests from one or more peripherals. It has an arbiter for handling the priority between DMA
requests. For more details, refer to "PrimeCell® μDMA Controller (PL230)" from the Technical
Reference Manual

19.2 Features

• 6 channels
• Each channel is connected to dedicated hardware DMA requests and software trigger is
also supported on each channel.
• Priorities between requests from the DMA channels are software programmable (2 levels
consisting of high, default)
• Memory-to-memory transfer (software request only)
• TCP/IP-to-memory transfer (software request only)
• SPI/UART-to-memory transfer (hardware request and software request)
• Access to Flash, SRAM, APB and AHB peripherals as source and destination

19.3 Functional description

Figure 17 shows the DMA block diagram.
CM0
AHB-Lite BUS
Interface
W7500x Reference Manual Version1.1.0
TCP/IP
SRAM
Flash SRAM
Controller
Flash SRAM
Figure 17. DMA Block diagram
GPIOA/GPIOB
GPIO x 16
GPIOC/GPIOD
APB
Bridge
uDMA
(PL230)
DMA request
Other
APB
Peripherals
SPI0
SPI1
UART0
UART1
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