Uart0Ibrd (Uart0 Integer Baud Rate Register); Uart0Fbrd (Uart0 Fractional Baud Rate Register) - Wiznet W7500 Reference Manual

These bits are cleared to 0 at reset.
Where, �� is nominally 1.8432MHz
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The divisor is 1.42MHz < ��
– 2.11us.

UART0IBRD (UART0 Integer Baud Rate Register)

Address offset: 0x0024
Reset value: 0x00
The UART0IBRD Register is the integer part of the baud rate divisor value.
31 30 29 28
res res res res
15 14 13 12
[15:0] BAUD DIVINT – The integer baud rate divisor.
These bits are cleared to 0 on reset

UART0FBRD (UART0 Fractional Baud Rate Register)

Address offset: 0x0028
Reset value: 0x00
The UART0FBRD register is the fractional part of the baud rate divisor value.
31 30 29 28
res res res res
15 14 13 12
res res res res
[5:0] BAUD DIVFRAC – The fractional baud rate divisor.
These bits are cleared to 0 on reset
The baud rate divisor is calculated as follows:
Baud rate divisor BAUDDIV = (��
Where, �� is the UART reference clock frequency.
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W7500x Reference Manual Version1.1.0
ILPDVSR = (��
< 2.12MHz, results in a low-power pulse duration of 1.41
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27 26 25 24
res res res res
11 10 9 8
BAUD DIVINT
27 26 25 24
res res res res
11 10 9 8
res res res res
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�������������� ����������������16
23 22 21
res res res
7 6 5
w
23 22 21
res res res
7 6 5
res res
/(16 × �������� ��������))
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20 19 18 17
res res res res
4 3 2 1
20 19 18 17
res res res res
4 3 2 1
BAUD DIVFRAC
w
332 / 399
16
res
0
16
res
0