Table 17 Pwm Channel 0 Register Map And Reset Values - Wiznet W7500 Reference Manual

Table 17 PWM channel 0 register map and reset values

Offset Register
PWMCH0IR
0x00
reset value
PWMCH0IER
0x04
reset value
PWMCH0ICR
0x08
reset value
PWMCH0TCR
0x0C
0 0 0 0
reset value
PWMCH0PCR
0x10
reset value
PWMCH0PR
0x14
reset value
PWMCH0MR
0x18
reset value 0 0 0 0
PWMCH0LR
0x1C
1 1 1 1
reset value
PWMCH0UDMR
0x20
reset value
PWMCH0TCMR
0x24
reset value
PWMCH0PEEER
0x28
reset value
PWMCH0CMR
0x2C
reset value
PWMCH0CR
0x30
reset value 0 0 0 0
PWMCH0PDMR
0x34
reset value
PWMCH0DZER
0x38
reset value
PWMCH0DZCR
0x3C
reset value
W7500x Reference Manual Version1.1.0
TCR
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0
1 1 1 1 1 1 1 1 1 1 1
0 0 0 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0 0 0 0 0
0
0
MR
0 0 0 0 0 0 0 0 0 0 0 0
LR
1 1 1 1 1 1 1 1 1 1 1 1
CR
0 0 0 0 0 0 0 0 0 0 0 0
DZC
0 0 0 0 0
비고
Channel-0 interrupt register
0 0 0
Channel-0 interrupt enable register
0 0 0
Channel-0 interrupt clear register
Write only register
Channel-0 Timer/Counter Register
0 0 0 0 0
Channel-0 Prescale Counter
PCR
Register
0 0 0 0 0
PR Channel-0 Prescale Register
0 0 0 0 0
Channel-0 Match Register
0 0 0 0 0
Channel-0 Limit Register
1 1 1 1 1
Channel-0 Up-Down Mode Register
0
Channel-0 Timer/Counter Mode
TCM
Register
0 0
Channel-0 PWM output Enable and
PEEE
External input Enable Register
0 0
Channel-0 Capture Mode Register
0
Channel-0 Capture Register
0 0 0 0 0
Channel-0 Periodic Mode Register
0
Channel-0 Dead Zone Enable
Register
0
Channel-0 Dead Zone Counter
Register
0 0 0 0 0
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