Table 37 Dma Trigger Points For The Transmit And Receive Fifos - Wiznet W7500 Reference Manual

Burst DMA transfer request, asserted by the SSP. This signal is asserted when

the receive FIFO contains four or more characters.
- SSPRXDMACLR
DMA request clear asserted by the DMA controller to clear the receive request

signals. If DMA burst transfer is requested, the clear signal is asserted during
the transfer of the last data in the burst.
Transmit – The DMA interface includes the following signals for transmit:
- SSPTXDMASREQ
Single-character DMA transfer request asserted by the SSP. This signal is

asserted when there is at least one empty location in the transmit FIFO.
- SSPTXDMABREQ
Burst DMA transfer request asserted by the SSP. This signal is asserted when

the transmit FIFO contains four characters or fewer.
- SSPTXDMACLR
DMA request clear asserted by the DMA controller to clear the transmit

request signals. If a DMA burst transfer is requested, the clear signal is
asserted during the transfer of the last data in the burst.
The burst transfer and single transfer request signals are not mutually exclusive. They can
both be asserted at the same time. For example, when there is more data than the watermark
level of four in the receive FIFO, the burst transfer request and the single transfer request are
asserted.
When the amount of data left in the receive FIFO is less than the watermark level, the single
request only is asserted. This is useful for situations when the number of characters left to be
received in the stream is less than a burst.
For example, if 19 characters must be received, the DMA controller then transfers four bursts
of four characters and three single transfers to complete the stream.
The PrimeCell SSP does not assert the burst request for the remaining three characters.
Each request signal remains asserted until the relevant DMA clear signal is asserted. After the
request clear signal is de-asserted, a request signal can become active again depending on the
conditions that previous sections describe. All request signals are de-asserted if the PrimeCell
SSP is disabled or the DMA enable signal is cleared.
Table 37 shows the trigger points for DMABREQ of both the transmit and receive FIFOs.

Table 37 DMA trigger points for the transmit and receive FIFOs.

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