Uart0Rsr/Ecr (Uart0 Receive Status Register/Error Clear Register) - Wiznet W7500 Reference Manual

The write operation initiates transmission from the UART. The data is prefixed with a start bit,
appended with the appropriate parity bit(if parity is enabled), and a stop bit. The resultant
word is then transmitted.
The received data byte is read by performing reads from the UARTDR register along with the
corresponding status information.
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res res res res
15 14 13 12
res res res res
[11] OE – Overrun error
0: data is empty
1: data is received and the receive FIFO is already full.
[10] BE – Break error
1: if a break condition was detected, indicating that the received data input was held
LOW of longer than a full-word transmission time(defined as start, data, parity and
stop bits)
[9] PE – Parity error
1: it indicates that the parity of the received, it indicates that the parity of the
received data character does not match the parity that the EPS and SPS bits in the line
control register, UARTLCR_H
[8] FE – Framing error
1: it indicates that the received
[7:0] DATA – Receive (READ)/Transmit (WRITE) data
UART0RSR/ECR (UART0 Receive Status Register/Error Clear
Register)
Address offset: 0x004
Reset value: 0x0000_0000
The UART0RSR/ECR is the receive status register/error clear register.
Receive status can also be read from the UART0RSR register.
A write to the UART0ECR register clears the framing, parity, break, and overrun errors.
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res res res res
W7500x Reference Manual Version1.1.0
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11 10 9 8
OE BE PE FE
R R R R
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7 6 5 4
DATA
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19 18 17
res res res
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R/W
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res
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res