Wiznet W7500 Reference Manual page 166

Ping-pong

See ARM micro DMA (PL230) documentation for additional cycle types.
For all cycle types, the controller arbitrates after 2
R
is set to a large 2 value then it prevents all other channels from performing a DMA transfer
until the low-priority DMA transfer completes. Therefore, the user must take care when setting
the R_power bit in the channel_cfg data structure, that the latency for high-priority channels
is not significantly increased.
Invalid cycle
After the controller completes a DMA cycle, it sets the cycle type to invalid to prevent it from
repeating the same DMA cycle.
Basic cycle
In this mode, the controller can be configured to use either the primary or the alternate
channel control data structure. After the channel is enabled and the controller receives a
request for this channel, the flow for basic cycle is as below:
1. The controller performs 2
If the number of transfers remaining is zero the flow continues at step 3.
2. The controller arbitrates:
- If a higher-priority channel is requesting service, then the controller services that
channel.
- If the peripheral or software signals a request to the controller, then it continues at
step 1.
3. The controller sets dma_done[c] signal for this channel HIGH for one system clock cycle.
This indicates to the host processor that the DMA cycle is complete.
Auto-request cycle
When the controller operates in this mode, it is only necessary to receive a single request to
enable the controller to complete the entire DMA cycle. This enables a large data transfer to
occur, without significantly increasing the latency for servicing higher priority requests or
requiring multiple requests from the processor or peripheral.
The auto-request cycle is typically used for memory-to-memory requests. In this case,
software generates the starting request for the 2
data structure.
W7500x Reference Manual Version1.1.0
R
R
transfers.
R
transfers after setting up the DMA control
DMA transfers. If a low-priority channel
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