Wiznet W7500 Reference Manual page 337

In other words, if a bit of UART0IMSC is '0', an interrupt will not be issued even if the
corresponding bit of interrupt register is '1'.
31 30 29 28 27
res res res res res
15 14 13 12
res Res res res
[10] OEIM – Overrun error interrupt mask
0: Disable UART0OEINTR
1: Enable UART0OEINTR
[9] BEIM – Break error interrupt mask
0: Disable UART0BEINTR
1: Enable UART0BEINTR
[8] PEIM – Parity error interrupt mask
0: Disable UART0EINTR
1: Enable UART0EINTR
[7] FEIM – Framing error interrupt mask
0: Disable UART0FEINTR
1: Enable UART0FEINTR
[6] RTIM – Receive timeout interrupt mask
0: Disable UART0RTINTR
1: Enable UART0RTINTR
[5] TXIM – Transmit interrupt mask
0: Disable UART0TXINTR
1: Enable UART0TXINTR
[4] RXIM – Receive interrupt mask
0: Disable UART0RXINTR
1: Enable UART0RXINTR
[3] DSRMIM – nUART0DSR modem interrupt mask
0: Disable UART0DSRINTR
1: Enable UART0DSRINTR
[2] DCDMIM – nUART0DCD modem interrupt mask
0: Disable UART0DCDINTR
1: Enable UART0DCDINTR
[1] CTSMIM – nUART0CTS modem interrupt mask
W7500x Reference Manual Version1.1.0
26 25 24 23
res res res res
11 10 9 8
res
OEIM BEIM PEIM
R/W R/W R/W
22 21 20 19
res res res res
7 6 5 4
FEIM RTIM TXIM RXIM
R/W R/W R/W R/W
18 17 16
res res res
3 2 1 0
DSR DCD CTS RIMI
MIM MIM MIM M
R/W R/W R/W R/W
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