Rtc Interrupt Pending Register (Rtcintp) - Wiznet W7500 Reference Manual

[6] AINT – RTC Alarm Interrupt Enable
This bit set and cleared by S/W to enable or disable RTC Alarm interrupt.
0 : No effect
1 : Alarm interrupt enabled

RTC Interrupt Pending register (RTCINTP)

Address offset: 0x0008
Reset value: 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
res res res res
Bit [0] RTCCIF – RTC Counter Interrupt pending flag
When one, the Counter Increment Interrupt block generated an interrupt. Writing a
one to this bit clears the counter increment interrupt.
Read 0 : No effect
Read 1 : an increment of the Second value generates an interrupt
Write 0 : No effect
Write 1 : clear interrupt
Bit [1] RTCALF – RTC Alarm interrupt pending flag
When one, the alarm registers generated an interrupt. Writing a one to this bit clears
the alarm interrupt.
Read 0 : No effect
Read 1 : an increment of the Minute value generates an interrupt
Write 0 : No effect
Write 1 : clear interrupt
W7500x Reference Manual Version1.1.0
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11 10 9 8
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23 22 21 20
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7 6 5 4
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