Pwm Channel-2 Registers (Base Address : 0X4000_5200); Channel-2 Interrupt Register(Pwmch2Ir); Channel-2 Interrupt Enable Register(Pwmch2Ier) - Wiznet W7500 Reference Manual

21.8 PWM Channel-2 Registers (Base address : 0x4000_5200)

Channel-2 interrupt register(PWMCH2IR)

Base address : 0x4000_5200
Address offset : 0x00
Reset value : 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
res res res res
[0] MI – Match Interrupt
This bit is set by hardware and cleared by interrupt clear register.
O : Match interrupt does not occur.
1 : Match interrupt occurs.
[1] OI – Overflow Interrupt
This bit is set by hardware and cleared by interrupt clear register.
O : Overflow interrupt does not occur.
1 : Overflow interrupt occurs.
[2] CI – Capture Interrupt
This bit is set by hardware and cleared by interrupt clear register.
O : Capture interrupt does not occur.
1 : Capture interrupt occurs.

Channel-2 interrupt enable register(PWMCH2IER)

Base address : 0x4000_5200
Address offset : 0x04
Reset value : 0x0000_0000
31 30 29 28
res res res res
15 14 13 12
res res res res
W7500x Reference Manual Version1.1.0
27 26 25 24
res res res res
11 10 9 8
res res res res
27 26 25 24
res res res res
11 10 9 8
res res res res
23 22 21 20
res res res res
7 6 5 4
res res res res
23 22 21 20
res res res res
7 6 5 4
res res res res
19 18 17 16
res res res res
3 2 1 0
res CI OI MI
R R R
19 18 17 16
res res res res
3 2 1 0
res CIE OIE MIE
R/W R/W R/W
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