Enable Primecell Ssp Operation; Clock Ratios - Wiznet W7500 Reference Manual

Enable PrimeCell SSP operation

You can either prime the transmit FIFO, by writing up to eight 16-bit values when the PrimeCell
SSP is disabled, or permit the transmit FIFO service request to interrupt the CPU. Once enabled,
transmission or reception of data begins on the transmit, SSPTXD, and receive, SSPRXD, pins.

Clock ratios

There is a constraint on the ratio of the frequencies of PCLK to SSPCLK. The frequency of
SSPCLK must be less or equal to that of PCLK. This ensures that control signals from the SSPCLK
domain to the PCLK domain are guaranteed to get synchronized before one frame duration:
FSSPCLK <= FPCLK.
In the slave mode of operation, the SSPCLKIN signal from the external master is double-
synchronized and then delayed to detect an edge. It takes three SSPCLKs to detect an edge
on SSPCLKIN. SSPTXD has less setup time to the falling edge of SSPCLKIN on which the master
is sampling the line.
The setup and hold times on SSPRXD, with reference to SSPCLKIN, must be more conservative
to ensure that it is at the right value when the actual sampling occurs within the SSPMS. To
ensure correct device operation, SSPCLK must be at least 12 times faster than the maximum
expected frequency of SSPCLKIN.
The frequency selected for SSPCLK must accommodate the desired range of bit clock rates.
The ratio of minimum SSPCLK frequency to SSPCLKOUT maximum frequency in the case of the
slave mode is 12, and for the master mode, it is two.
To generate a maximum bit rate of 1.8432Mbps in the master mode, the frequency of SSPCLK
must be at least 3.6864MHz. With an SSPCLK frequency of 3.6864MHz, the SSPCPSR register
must be programmed with a value of 2, and the SCR[7:0] field in the SSPCR0 register must be
programmed with a value of 0.
To work with a maximum bit rate of 1.8432Mbps in the slave mode, the frequency of SSPCLK
must be at least 22.12MHz. With an SSPCLK frequency of 22.12MHz, the SSPCPSR register can
be programmed with a value of 12 and the SCR[7:0] field in the SSPCR0 register can be
programmed with a value of 0. Similarly, the ratio of SSPCLK maximum frequency to
SSPCLKOUT minimum frequency is 254 x 256.
The minimum frequency of SSPCLK is calculated by the following equations, both of which
must be satisfied:
F (min) => 2 x F
SSPCLK
W7500x Reference Manual Version1.1.0
(max), for master mode
SSPCLKOUT
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