Ssp1 Control Register 1 (Ssp1Cr1) - Wiznet W7500 Reference Manual

This is applicable to Motorola SPI frame format only.
[15:8] SCR – Serial clock rate
The value SCR is used to generate the transmit and receive bit rate of the SSP. The bit
rate is:
fSSPCLK / (CPSDVSR * (1 + SCR))
where
CPSDVSR is an even value from 2-254, programmed through the SSPCPSR register and
SCR is a value from 0-255.

SSP1 Control register 1 (SSP1CR1)

Address offset: 0x0004
Reset value: 0x0000_0000
31 30 29 28
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15 14 13 12
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[0] LBM – Loop back mode:
0 : normal serial port operation enabled
1 : output of transmit serial shifter is connected to input of receive serial
shifter internally
[1] SSE – Synchronous serial port enable:
0 : SSP1 operation disabled.
1 : SSP1 operation enabled.
[2] MS – Master or Slave mode select:
0 : device configured as master, default.
1 : device configured as slave.
[3] SOD – Slave-mode output disable.
This bit is relevant only in the slave mode, MS = 1. In multiple-slave systems, it is
possible for a SSP1 master to broadcast a message to all slaves in the system while
ensuring that only one slave drives data onto its serial output line. In such systems the
RXD lines from multiple slaves could be tied together.
To operate in such systems, the SOD bit can be set if the SSP1 slave is not supposed to
drive the SSPTXD line:
0 : SSP1 can drive the SSPTXD output in slave mode.
W7500x Reference Manual Version1.1.0
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11 10 9 8
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7 6 5 4
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3 2 1 0
SOD MS SSE LBM
R/W R/W R/W R/W
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