Rtc Interrupt Mask Register (Rtcinte) - Wiznet W7500 Reference Manual

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[0] CLKEN – Clock Enable
This bit written by S/W to enable or disable clock
0 : The time counters are disabled (clock stop)
1 : The time counters are enabled (clock enable)
[1] DIVRST – RTC Divider Reset
This bit set and cleared by S/W to reset RTC divider.
0 : No effect
1 : When 1, divider reset and remain reset until RTCCON[1] is changed to 0.
[5] INTEN – RTC Interrupt Enable
This bit set and cleared by S/W to enable or disable RTC interrupt.
0 : RTC Interrupt is disabled
1 : RTC Interrupt is enabled

RTC Interrupt Mask register (RTCINTE)

Address offset: 0x0004
Reset value: 0x0000_0000
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[0] IMSEC – RTC Second Interrupt Enable
This bit set and cleared by S/W to enable or disable RTC Second interrupt.
0 : No effect
1 : an increment of the Second value generates an interrupt
[1] IMMIN – RTC Minute Interrupt Enable
W7500x Reference Manual Version1.1.0
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res res INTEN res
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AIN IMM
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