Wiznet W7500 Reference Manual page 192

External
Input
Start/Stop
Register
Rising edge
detect
Falling edge
detect
Timer/Counter 0
Figure 29 Counter mode with rising and falling edge
Prescaler description
The PWM has 6-bit prescale counter(PC) and the prescaler can divide the Timer/Counter clock
frequency. Users can control it by Prescale Register(PR).
Figure 30 and Figure 31 shows some examples of the Timer/Counter timing with prescale
register is 2, match register is 2, limit register is 12, timer mode, periodic mode, up-count
mode, and no interrupt clear.
PWMCLK
Start/Stop
Register
Prescale
Counter
Timer/Counter
Prescale Counter
Overflow
Match Interrupt
Interrupt
Register[2:0]
Figure 30 Timer/Counter timing diagram with match interrupt
W7500x Reference Manual Version1.1.0
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