Uart0Lcr_H (Uart0 Line Control Register) - Wiznet W7500 Reference Manual

The BAUDDIV is comprised of the integer value (BAUD DIVINT) and the fractional value (BAUD
DIVFRAC).
Example 1
If the required baud rate is 115200 and UARTCLK = 8MHz then:
Baud rate divisor = (8 × 10
This means BRD = 4 and BRD
��
(Therefore, UART0IBRD = 4)
Therefore, UART0FBRD = inerger[ ( 0.340278 × 64 ) + 0.5] = 22
Generated baud rate divider = UART0IBRD + (UART0FBRD/64) = 4.34375
Generated baud rate = (8 × 10
Error = (115108 − 115200)/(115200) × 100 = -0.07861%
When UartCLK = 8MHz
Integer divisor
0x2
0x4
0x6
0x8
0x22

UART0LCR_H (UART0 Line Control Register)

Address offset: 0x002C
Reset value: 0x00
The UART0LCR_H register is the line control register. This register accesses bits 29 to 22 of
the UART line control register, UART0LCR.
31 30 29 28
res res res res
15 14 13 12
res res res res
[7] SPS – Stick parity select
0: stick parity is disable
1: either:
W7500x Reference Manual Version1.1.0
6
)/(16 × 115200) = 4.340278
= 0.340278
��
6
)/(16 × 4.34375) = 115107.914
Fractional Required bit
divisor rate(bps)
0x0B 230400
0x16 115200
0x21 76800
0x2C 57600
0x2E 14400
27 26 25 24
res res res res
11 10 9
res res res res
Generated bit
rate(bps)
2.171875
4.34375
6.515625
8.6875
34.71875
23 22 21
res res res
8 7 6 5
SPS WLEN
R/W
Error%
-0.07994
-0.07994
-0.07994
-0.07994
0.010001
20 19 18 17
res res res res
4 3 2 1
FEN STP2 EPS PEN
333 / 399
16
res
0
BRK